Approximate arithmetic units under voltage under-scaling

Increasingly power hungry processors and the identification of error tolerant applications have made approximate computing techniques one of the researching scopes of the present. The main objective of this work is to study and assess the benefits of certain approximate arithmetic units for their inclusion in the DRAC project?s approximate accelerator. In order to accomplish this objective, different approximate and accurate adders and multipliers are implemented in Verilog, synthesized and simulated using Cadence tools and finally compar- ed between them to evaluate whether they offer any benefits or not. Simulations are performed for both Overclocking and Voltage Underscaling conditions. The results indicated that some of the approximate adders show very competitive precision values at overclocking simulations for 400 ps, with slightly better power results, and other adders also presented very encouraging results for voltage overscaling simulations, offering higher precision values than the accurate adders for 0.4V. In contrary, the multipliers exhibited worse results than the accurate ones in every aspects for the realistic case dataset provided by the SW team