High-speed structures for dynamically clocked and multi-clock systems

With an ever-decreasing minimum feature size, integrated circuits have more transistors, run faster and are larger than ever before. As a result, problems such as heat dissipation, clock generation and clock distribution are at the forefront of challenges facing chip designers today. A Globally Asynchronous, Locally Synchronous (GALS) system combined with dynamic voltage and frequency scaling is an architecture that can combat many of these issues while allowing for high performance operation. In this thesis, we investigate three distinct circuit designs compatible with, but not limited to, such a system. The first uses a novel bi-directional asynchronous FIFO to communicate between independently-clocked synchronous blocks. The second is an All-Digital Dynamic Clock Generator designed to glitchlessly switch between frequencies with very low latency. The third is a Digitally-Controlled Oscillator that can either be used stand-alone or as part of an all-digital PLL (ADPLL) to generate the global fixed frequency clocks required by the All-Digital Dynamic Clock Generator. These designs have been designed, simulated and shown to perform all the tasks required to implement a Globally Asynchronous, Locally Dynamic System (GALDS) in either a traditional ASIC design or a newer System-on-Chip (SoC)