We investigate the existence and computability of a fault cover for a configuration architecture; that is, a setting of switches that achieves an array despite the presence of faulty elements and broken interconnect. The switches may be stuck open or closed. For a preponderance of architectures these questions are NP-complete. This is not the case with local sparing, a fundamental approach that can, in fact, be applied to any nominal architecture. We give an algorithm that decides and computes a fault cover in time that is subcubic in the size of a locally spared array whose neighboring blocks of h elements each can be connected in any of h x h ways.We measure scaling in terms of the probability of a fault cover (coverage), the fraction of ...
This paper presents constructions for fault-tolerant two-dimensional mesh architectures. The constr...
This thesis examines three specific issues of defect-tolerant VLSI: (1) design and reconfiguration o...
The general capabilities of fault tolerant computations in one-way and two-way linear cellular array...
With few exceptions, the two issues of algorithm design and fault tolerance for processor arrays hav...
Switching lattices are two-dimensional arrays composed by four-terminal switches (crossbar arrays). ...
Switching lattices are two-dimensional arrays composed by four-terminal switches (crossbar arrays). ...
Switching lattices are two-dimensional arrays composed by four-terminal switches (crossbar arrays). ...
Switching lattices are two-dimensional arrays composed by four-terminal switches (crossbar arrays). ...
. Fault tolerance through the incorporation of redundancy and reconfiguration is quite common. In a ...
163 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1985.The concept of algorithm-base...
AbstractAchieving fault tolerance through incorporation of redundancy and reconfiguration is quite c...
Abstract. The general capabilities of fault tolerant computations in one-way and two-way linear cell...
We present an efficient method for tolerating faults in a two-dimensional mesh architecture. Our app...
This paper presents constructions for fault-tolerant two-dimensional mesh architectures. The constr...
In this paper we consider the problem of reconfiguring processor arrays subject to computational loa...
This paper presents constructions for fault-tolerant two-dimensional mesh architectures. The constr...
This thesis examines three specific issues of defect-tolerant VLSI: (1) design and reconfiguration o...
The general capabilities of fault tolerant computations in one-way and two-way linear cellular array...
With few exceptions, the two issues of algorithm design and fault tolerance for processor arrays hav...
Switching lattices are two-dimensional arrays composed by four-terminal switches (crossbar arrays). ...
Switching lattices are two-dimensional arrays composed by four-terminal switches (crossbar arrays). ...
Switching lattices are two-dimensional arrays composed by four-terminal switches (crossbar arrays). ...
Switching lattices are two-dimensional arrays composed by four-terminal switches (crossbar arrays). ...
. Fault tolerance through the incorporation of redundancy and reconfiguration is quite common. In a ...
163 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1985.The concept of algorithm-base...
AbstractAchieving fault tolerance through incorporation of redundancy and reconfiguration is quite c...
Abstract. The general capabilities of fault tolerant computations in one-way and two-way linear cell...
We present an efficient method for tolerating faults in a two-dimensional mesh architecture. Our app...
This paper presents constructions for fault-tolerant two-dimensional mesh architectures. The constr...
In this paper we consider the problem of reconfiguring processor arrays subject to computational loa...
This paper presents constructions for fault-tolerant two-dimensional mesh architectures. The constr...
This thesis examines three specific issues of defect-tolerant VLSI: (1) design and reconfiguration o...
The general capabilities of fault tolerant computations in one-way and two-way linear cellular array...