A scheme for built-in self test of a digital integrator /

In conventional built-in self test (BIST) schemes, additional hardware is normally added to the original circuit for test pattern generation and compaction of test responses. This additional hardware not only adds significant hardware overhead, but also degrades performance, which cannot be tolerated in high performance architectures such as data-path architectures.Accumulator-Based Compaction (ABC) is a recently introduced test response compaction scheme which targets a broad class of circuits featuring data-path architectures. ABC uses existing arithmetic hardware commonly available in such circuits to perform compaction of test responses with little or no modification to the circuit under test (CUT). This implies little or no area overhead or performance degradation.A scheme based on ABC is introduced to test an integrator circuit commonly used to perform decimation in signal processing systems. The integrator suffers from poor testability due to the nature of the inputs supplied to it. Minor modifications to the circuit are proposed which enhance testability significantly, with negligible area overhead and no performance degradation. Those modifications also allow the CUT itself to be used for test pattern generation and test response compaction. Monte-Carlo simulations are used to verify the complete fault coverage attained after implementation of the suggested modifications. Furthermore, experiments based on measure of the average entropy, namely state coverage and transition coverage, are used to heuristically measure the testability of the circuit independent of a specific fault model