Automated fault diagnosis and empirical validation of fault models in CMOS VLSI circuits

The selection of adequate fault models is crucial to generating tests of high quality for complex digital VLSI circuits. This thesis presents a methodology to perform empirical validation of fault models and to get measures of effectiveness of test sets based on the targeted fault models.The methodology is based on the automated fault diagnosis of test circuits, representative of the class of circuits being studied and designed to capture the characteristics of the fabrication process, cell libraries and CAD tools used in their development.The methodology is applied to study the faulty behaviour of random logic environments for an experimental VLSI fabrication process. A test circuit is designed, using CMOS technology, and a statistically significant number of samples fabricated. The samples are tested and, subsequently, diagnosed, using a set of software tools developed for the purpose. Results of the ensuing analysis are presented