Interprocessor communication supports for a multiprocessor dataflow machine

The dataflow model of computation offers a powerful alternative to the von Neumann based model for exploiting the fine-grain parallelism inherent in scientific computations. Under this model, a program is expressed in the form of a graph, where the data values are carried by tokens, moving on the arcs of the graph. A distinctive feature of dataflow computers is the absence of the conventional program counter. Instead, instruction execution is solely determined by the availability of data which provides ample instruction level fine-grain parallelism. A highly pipelined static dataflow architecture has recently been proposed, based on the argument fetching principle, yielding the McGill Dataflow Architecture (MDFA).In this thesis, an inter-processor communication mechanism is proposed. With this mechanism, a multiprocessor MDFA system can be constructed, based on a distributed memory organization. An efficient inter-processor synchronization and communication support is presented, for sending and receiving data through an interconnection network. An Interprocessor Communication Unit (ICU) has been designed to implement the above mechanism in the MDFA. A simulation testbed has been implemented to study the performance of the multiprocessor. It includes an assembler, with multiprocessor extensions, and a multiprocessor simulator. An analysis based on the simulations results is presented, focusing on the impact of long latency operations on program performance