A logic minimization algorithm for synthesis of strictly irredundant networks /

Many efficient ways for two-level logic minimization of Boolean functions have been presented. They can obtain the minimum number of product terms and no product terms can be replaced by a product term with fewer variables. But the minimal result obtained from the previous cube-based algorithm is prime and irredundant only for some of the connected outputs and therefore the network that results from the multilevel synthesis might have redundancy and hence untestability.In this thesis, we present a logic minimization algorithm for synthesis of strictly irredundant networks. The key point is that any stuck-at fault in the two-level minimized network should be propagated to every output which is connected. This algorithm is based on the concept of PLA testing and fault simulation