An optoelectronic-VLSI chip with forward error correction to improve the reliability of parallel optical data links /

Parallel optical interconnects (POIs) promise to deliver tremendous gains in bandwidth for applications such as massively parallel computing systems and telecommunication switches. At the core of any interconnect solution lies the fundamental problem of reliable transmission. Next-generation optical communication designers are running into hard limits when it comes to increasing data transmission rates and reducing errors. These two factors are typically in opposing balance: minimize bit error rate (BER) and data rates suffer, increase transmission rates and data integrity is compromised.To answer these design challenges, this thesis proposes to use forward error correction (FEC) codes in an attempt to simultaneously improve data throughput, reduce BER and reduce power consumption. To verify that this is indeed possible, an optoelectronic-VLSI (OE-VLSI) chip with a FEC module was implemented in CMOS. This chip was designed in the context of a POI prototype system to demonstrate 1080 optical interconnections between two OE-VLSI chips