In order to reduce the test development cost and guarantee testable designs, it is essential to have synthesis transformations that are testability and test-set preserving. In this thesis, we study testability preservation of transformations that form the basis of existing state-of-the-art logic synthesis and optimization techniques.We show that the concurrent decomposition and factorization transformations, except dual-extraction of multiplexor structures, preserve testablility and test-set under several testing constraints. Furthermore, we provide sufficient conditions for test-set preservation under the algebraic resubstitution with complement transformation that cover a larger class of complementary expressions than was known previously...
During synthesis of circuits for Boolean functions area, delay and testability are optimization goal...
The feasibility of generating high quality functional test vectors for sequential circuits using the...
This paper presents a testable synthesis methodology applicable to any top-down design method based ...
Computer-aided design tools, which aim at a satisfactory tradeoff of conflicting design objectives, ...
Abstract| Recently, it has been shown that retiming has a very strong impact on the run time of sequ...
It is well known that optimal logic synthesis can ensure fully testable combinational logic designs....
In this paper we continue to investigate the impact of logic synthesis on the testability of sequent...
Test generation for sequential VLSI circuits has remained a formidable problem to solve. The problem...
Abstract: A new approach to optimize multi-level logic circuits is introduced. Given a multi-level c...
We present a novel, highly efficient functional test generation methodology for synchronous sequenti...
poses a difficult problem for circuits implemented from finite-state ma-chines. The flip-flops in se...
Diagnosis is an important but difficult problem in the design and manufacturing of VLSI circuits. Th...
This thesis presents a new concurrent method for the decomposition and factorization of Boolean expr...
Multilevel Logic Optimization Transformations used in existing logic synthesis systems are character...
During synthesis of circuits for Boolean functions area, delay and testability are optimization goal...
During synthesis of circuits for Boolean functions area, delay and testability are optimization goal...
The feasibility of generating high quality functional test vectors for sequential circuits using the...
This paper presents a testable synthesis methodology applicable to any top-down design method based ...
Computer-aided design tools, which aim at a satisfactory tradeoff of conflicting design objectives, ...
Abstract| Recently, it has been shown that retiming has a very strong impact on the run time of sequ...
It is well known that optimal logic synthesis can ensure fully testable combinational logic designs....
In this paper we continue to investigate the impact of logic synthesis on the testability of sequent...
Test generation for sequential VLSI circuits has remained a formidable problem to solve. The problem...
Abstract: A new approach to optimize multi-level logic circuits is introduced. Given a multi-level c...
We present a novel, highly efficient functional test generation methodology for synchronous sequenti...
poses a difficult problem for circuits implemented from finite-state ma-chines. The flip-flops in se...
Diagnosis is an important but difficult problem in the design and manufacturing of VLSI circuits. Th...
This thesis presents a new concurrent method for the decomposition and factorization of Boolean expr...
Multilevel Logic Optimization Transformations used in existing logic synthesis systems are character...
During synthesis of circuits for Boolean functions area, delay and testability are optimization goal...
During synthesis of circuits for Boolean functions area, delay and testability are optimization goal...
The feasibility of generating high quality functional test vectors for sequential circuits using the...
This paper presents a testable synthesis methodology applicable to any top-down design method based ...