Packaging of two dimensional optoelectronic device arrays for optical backplanes

The use of existing packaging techniques for microelectronics are studied in terms of their applicability to the packaging of optoelectronic device arrays for photonic inter-connect applications. In particular, the packaging of smart pixel arrays for free-space optical backplanes is quantitatively explored. This assessment is made from three basic perspectives: thermal management capabilities, connectivity and bandwidth, and alignment to a free-space optical system. In the assessment, a smart pixel array design space analysis is derived which shows that, by constraining the smart pixel array characteristics, the use of existing packaging technologies is possible. This leads to the derivation of expressions which relate both system and smart pixel array parameters to representative packaging parameters. It is seen in the analysis that while the thermal management imposes constraints on the window size, smart pixel density and size, the alignment imposes constraints mostly on the window size. The architectural characteristics of the smart pixel array are mostly affected by the connectivity and bandwidth of the packaging technology.The integration of packaged smart pixel arrays into optical backplane demonstrators is also discussed, and the design and implementation of an optical backplane demonstrator is presented. This is complemented by the design, implementation and characterization of an optomechanical assembly which uses the interface between a single chip carrier and a socket to provide means of alignment in three degrees of freedom. Pre-aligned and modular plug-in device array integration is demonstrated