FPGA driven synthesis employing a self-testing VLSI controller implementation as a case study

This thesis formulates, and implements an automotive Anti-lock Brake System (ABS), reporting on its design simulation, synthesis, and eventual layout steps, from which extensions are drawn towards digital onto controllers FPGA technology, and the potential migration of the design onto ASIC technology. Implementation/environment fine-tuning of embedded controllers as such necessitate quickly prototyped circuit realizations. Examination of its functionality, real-time response, implementation, and testability is performed in an attempt to measure the usefulness of higher level design entry facilities such as VHDL in a rapid prototyping environment. Continuous on-line testing is included using aperiodic sample injections where the resultant generated values are compared to signatures known a priori, without compromising functionality. The achievable area and timing aid in the determination of the efficiency of the process and provide fuel for an FPGA and/or ASIC migration path for eventual implementation. Commentaries and generalized methodologies are assembled from the design's simulation, synthesis and layout utilizing VHDL and FPGAs, illustrating CAD tool capabilities/requirements/limitations, with respect to real-time synthesis and rapid prototyping of general controller applications involving asynchronous elements. (Abstract shortened by UMI.