BIST fault diagnosis in scan-based modules

Testing digital devices constitutes a major portion of the cost and effort involved in their design, production, and use. Built-In Self-Test (BIST) has been warmly embraced by the Integrated Circuits (IC) industry as a solution for the continuously aggravating testing problem. BIST provides a simple go/no-go test screening answer. However, when test fall-out is high, it becomes necessary to diagnose faults to improve the yield.Signature Analysis (SA) is typically used in a BIST environment to compact the outputs of a module into a final signature. Several SA-based diagnostic schemes have been developed in the past. An overwhelming majority of these techniques assume the presence of very few error bits in the Test Response Sequence (TRS). However, this assumption is generally unrealistic since a faulty device in a practical BIST environment can generate an enormous number of erroneous bits in the TRS.In this thesis, a comprehensive survey of the current SA-based BIST diagnostic schemes is presented first. Then, novel BIST fault diagnosis techniques for scan-based VLSI modules are presented, based on multiple signature analysis. (Abstract shortened by UMI.