Transport triggered architecture processors may have function unit input registers, which allow operands to be written to function units earlier than the clock cycle where the operation begins execution. An operand used in consecutive operations may be written only once, saving register file accesses and internal bus traffic. This optimization is called operand sharing. In this paper, the effectiveness of operand sharing is analyzed from the perspective of improving the energy-efficiency of the processor. On average of 12.0 % and at the best case of 32.4 % of register file reads could be eliminated, resulting in the best case power savings of 5.3% and energy savings of 8.8 %. In one of the 14 measured cases, operand sharing allowed a regist...
Superscalar processors contain large, complex structures to hold data and instructions as they wait ...
Abstract. In order to reduce register file's peak temperature in an embedded processor we propo...
The storage for speculative values in superscalar processors is one of the main sources of complexit...
Register files represent a substantial portion of the energy budget in modern processors, and are gr...
Several studies and recent real world designs have promoted sharing of underutilized resources betwe...
In a modern processor architecture the register file (RF) consumes considerable amount of power. The...
Abstract—Several studies and real world designs have advocated the sharing of large execution units ...
Transport Triggered Architecture (TTA) processors allow unique low level compiler optimizations such...
In modern architectures the register file is one of the most energy consuming and frequently used co...
In modern processor architectures, the register file (RF) consumes considerable amount of the proces...
Abstract—In modern processor architectures, the register file (RF) consumes considerable amount of t...
In a modern processor architecture the register ??le (RF) consumes considerable amount of power. The...
Abstract. Modern microprocessor designs implement register renaming using register alias tables (RAT...
The complexity of the register file is currently one of the main factors on determining the cycle ti...
The register file is a power-hungry device in modern architectures. Current research on compiler tec...
Superscalar processors contain large, complex structures to hold data and instructions as they wait ...
Abstract. In order to reduce register file's peak temperature in an embedded processor we propo...
The storage for speculative values in superscalar processors is one of the main sources of complexit...
Register files represent a substantial portion of the energy budget in modern processors, and are gr...
Several studies and recent real world designs have promoted sharing of underutilized resources betwe...
In a modern processor architecture the register file (RF) consumes considerable amount of power. The...
Abstract—Several studies and real world designs have advocated the sharing of large execution units ...
Transport Triggered Architecture (TTA) processors allow unique low level compiler optimizations such...
In modern architectures the register file is one of the most energy consuming and frequently used co...
In modern processor architectures, the register file (RF) consumes considerable amount of the proces...
Abstract—In modern processor architectures, the register file (RF) consumes considerable amount of t...
In a modern processor architecture the register ??le (RF) consumes considerable amount of power. The...
Abstract. Modern microprocessor designs implement register renaming using register alias tables (RAT...
The complexity of the register file is currently one of the main factors on determining the cycle ti...
The register file is a power-hungry device in modern architectures. Current research on compiler tec...
Superscalar processors contain large, complex structures to hold data and instructions as they wait ...
Abstract. In order to reduce register file's peak temperature in an embedded processor we propo...
The storage for speculative values in superscalar processors is one of the main sources of complexit...