VLSI Implementation of Low Latency IEEE 802.11i Cryptography Processing Unit

IEEE 802.11i為無線區域網路的安全標準規格，並定義了三種與資料保密性有關的演算法，即WEP、TKIP與CCMP。WEP與TKIP的加解密核心為RC4演算法，而CCMP的加解密核心採用AES演算法。RC4演算法與AES演算法都屬於對稱式加密法的一種，此加密法的特性是傳送端與接收端須共享一把相同的祕密金鑰，才能達到資料的保密性。 在本論文的研究中，我們使用了Verilog硬體描述語言來實現IEEE 802.11i的加解密硬體架構，並依照cell-based流程來設計與驗証。由於RC4演算法的硬體實現需使用到一個記憶體，所以我們利用Artisan Standard Library SRAM Generator來產生。對於要加密的一個封包，不論封包長度為多少位元組，RC4有其一固定的延遲週期，此延遲會造成過低的資料吞吐量，尤其是當封包長度愈短時。因此在設計上，我們使用[8]中所提出的16-bit packed記憶體演算法來減少RC4的固定延遲週期，以提升加密時整體的資料吞吐量。在AES演算法方面，由於IEEE 802.11傳輸資料以1-byte為單位，因此使用原始128-bit的硬體架構來設計AES，將造成不必要的面積成本。取而代之，我們採用了32-bit的AES硬體架構來節省面積。 最後，在電路合成方面，我們透過Synopsys Design Compiler在TSMC 0.18um的製程下完成。合成後的面積在不包含記憶體的情況下，閘數量約為44,300，最高工作頻率約為51MHz，而在50MHz的頻率下所測得的功率消耗為12.61mW。IEEE 802.11i is the security standard specification of wireless local area network, and it defines three algorithms which are related to the data confidentiality, that is, WEP, TKIP, and CCMP. The cipher core of the WEP and TKIP is the RC4 algorithm while the cipher core of the CCMP is the AES algorithm. Both of the RC4 and AES algorithms are one of the symmetric ciphers, whose feature is that the transmitter and the receiver must share one same secret key to achieve the data confidentiality. In the research of this thesis, we use Verilog hardware description language to model and implement the cipher architecture of the IEEE 802.11i, then we use the cell-based design flow to verify our design. Since the hardware implementation of the RC4 algorithm needs to use a memory, we generate the memory with the Artisan Standard Library SRAM Generator. For a ciphered packet, regardless of the length of the packet data bytes, the RC4 has a constant latency which will generate the excessively low throughput when the packet length is too short especially. Therefore, in our implementation, we use the 16-bit packed memory algorithm proposed by [8] to reduce the constant latency in the RC4 algorithm, and the 16-bit packed memory algorithm can improve the overall throughput in the encryption. As for the AES algorithm, due to the byte-wise data transmission in the IEEE 802.11, the design will produce the unnecessary area cost if we implement the AES algorithm with the conventional 128-bit architecture. In place of the 128-bit architecture, we employ the 32-bit AES architecture to reduce the area cost. Finally, we synthesize our architecture through the Synopsys Design Compiler in the TSMC 0.18um process. If we don't take the memory into account, the residual area after the synthesis is about 44,300 gate counts, and the maximum frequency is approximately 51MHz, and then the power consumption at 50MHz frequency is 12.61mW.誌謝.........................................................................................................................i 中文摘要................................................................................................................ii 英文摘要...............................................................................................................iii 目錄.......................................................................................................................iv 表目錄..................................................................................................................vii 圖目錄.................................................................................................................viii 第一章 簡介........................................................................................................1 1.1 前言........................................................................................................1 1.2 MAC訊框格式......................................................................................2 1.3 對稱式加密法........................................................................................2 1.4 AES演算法............................................................................................3 第二章 先前相關的IEEE 802.11i架構研究[8] ...............................................8 第三章 RC4演算法與硬體架構設計..............................................................13 3.1 RC4演算法..........................................................................................13 3.1.1 基本演算法................................................................................13 3.1.2 16-bit Packed記憶體演算法[8] ...............................................14 3.2 RC4硬體架構設計..............................................................................16 3.2.1 使用單埠256×8-bit記憶體設計RC4 PRNG...........................17 3.2.1.1 記憶體初始化階段的運作.............................................18 3.2.1.2 記憶體排列階段的運作.................................................18 3.2.1.3 金鑰串流產生階段的運作.............................................18 3.2.2 使用單埠128×16-bit記憶體設計RC4 PRNG.........................19 3.2.2.1 記憶體初始化階段的運作.............................................20 3.2.2.2 記憶體排列階段的運作.................................................20 3.2.2.3 金鑰串流產生階段的運作.............................................20 第四章 IEEE 802.11i的加解密原理................................................................22 4.1 WEP加解密原理.................................................................................22 4.2 TKIP加解密原理................................................................................24 4.2.1 TKIP加密程序..........................................................................24 4.2.2 TKIP解密程序..........................................................................25 4.2.3 TKIP MPDU格式......................................................................26 4.2.4 TKIP MIC..................................................................................27 4.2.5 TKIP 混合函數.........................................................................29 4.3 CCMP加解密原理..............................................................................30 4.3.1 CCM模式..................................................................................31 4.3.1.1 CCM模式的確認性........................................................32 4.3.1.2 CCM模式的保密性........................................................33 4.3.2 CCMP協定................................................................................35 4.3.2.1 CCMP MPDU格式.........................................................35 4.3.2.2 CCMP加密程序..............................................................35 4.3.2.3 建構AAD........................................................................36 4.3.2.4 建構Nonce與CCMP標頭.............................................37 4.3.2.5 CCMP解密程序..............................................................37 4.3.2.6 CCMP結論......................................................................38 第五章 硬體實作與架構設計..........................................................................39 5.1 IEEE 802.11i加解密處理單元硬體架構............................................39 5.2 WEP/TKIP加解密硬體架構...............................................................42 5.2.1 rc4keygen模組..........................................................................46 5.2.1.1 rc4keygen模組在WEP模式下的運作方式..................46 5.2.1.2 rc4keygen模組在TKIP模式下的運作方式..................47 5.2.2 rc4core模組...............................................................................51 5.2.3 cipher模組.................................................................................52 5.2.4 cipMux模組...............................................................................53 5.2.5 p2s模組......................................................................................54 5.2.6 crc模組......................................................................................55 5.2.7 crcMux模組...............................................................................57 5.2.8 crcCtrl模組................................................................................57 5.2.9 michael模組..............................................................................58 5.2.9.1 micBuf模組.....................................................................59 5.2.9.2 micBlock模組.................................................................60 5.2.10 micMux模組............................................................................61 5.2.11 micCtrl模組.............................................................................62 5.2.12 mic2crc模組............................................................................63 5.2.13 icvCpr模組..............................................................................64 5.2.14 micCpr模組.............................................................................65 5.2.15 finishGen模組.........................................................................66 5.3 CCMP加解密硬體架構......................................................................67 5.3.1 ccmcore模組.............................................................................68 5.3.2 aes32模組..................................................................................73 第六章 實作結果與比較..................................................................................76 6.1 不同的RC4 PRNG硬體架構之實作結果比較.................................76 6.2 合成結果與比較..................................................................................77 6.3 資料吞吐量..........................................................................................78 6.3.1 WEP/TKIP資料路徑與所需的工作週期................................78 6.3.2 CCMP資料路徑與所需的工作週期.......................................80 第七章 結論與未來工作..................................................................................84 參考文獻..............................................................................................................8