The design of an all-digital VCO-based ADC in a 65nm CMOS technology

This thesis explores the study and design of an all-digital VCO-based ADC in a 65 nm CMOS technology. As the CMOS process enters the deep submicron region, the voltage-domain-based ADCs begins to suffer in improving their performance due to the use of complex analog components. A promising solution to improve the performance of an ADC is to employ as many as possible digital components in a time-domain-based ADC, where it uses the time resolution of an analog signal rather than the voltage resolution. In comparison, as the CMOS process scales down, the time resolution of an analog signal has found superior than the voltage resolution of an analog signal. In recent years, such time-domain-based ADCs have been taken an immense interest due to its inherent features and their design reasons. In this thesis work, the VCO-based ADC design, falls under the category of time-based ADCs which consists of a VCO and an appropriate digital processing circuitry. The employed VCO is used to convert a voltage-based signal into a time signal and thereby it also acts as a time-based quantizer. Then the resulting quantized-time signal is converted into a digital signal by an appropriate digital technique. After different architecture exploration, a conventional VCO-based ADC architecture is implemented in a high-level model to understand the characteristic behaviour of this time-based ADC and then a comprehensive functional schematic-level is designed in reference with the implemented behavioural model using cadence design environment. The performance has been verified using the mixed-levels, of transistor and behavioural-levels due to the greater simulation time of the implemented design. ADC’s dynamic performance has been evaluated using various experiments and simulations. Overall, the simulation experiments showed that the design was found to reach an ENOB of 4.9-bit at 572 MHz speed of sample per second, when a 120 MHz analog signal is applied. The achieved peak performance of the design was a SNR of 40 dB, SFDR of 34 dB and an SNDR of 31 dB over a 120 MHz BW at a 1 V supply voltage. Without any complex building blocks, this VCO-based all-digital ADC design provided a key feature of inherent noise shaping property and also found to be well compatible at the deep submicron region