A Study of Successive Approximation Registers and Implementation of an Ultra-Low Power 10-bit SAR ADC in 65nm CMOS Technology

In recent years, there has been a growing need for Successive Approximation Register (SAR) Analog-to-Digital Converter in medical application such as pacemaker. The demand for long battery life-time in these applications poses the requirement for designing ultra-low power SAR ADCs. This thesis work initially investigates and compares different structures of SAR control logics including the conventional structures and the delay line based controller. Additionally, it focuses on selection of suitable dynamic comparator architecture. Based on this analysis, dynamic two-stage comparator is selected due to its energy efficiency and capability of working in low supply voltages. Eventually, based on these studies an ultra-low power 10-bit SAR ADC in 65 nm technology is designed. Simulation results predict that the ADC consumes 12.4nW and achieves an energy efficiency of 14.7fJ/conversion at supply voltage of 1V and sampling frequency of 1kS/s. It has a signal-to-noise-and-distortion (SINAD) ratio of 60.29dB and effective-number-of-bits (ENOB) of 9.72 bits. The ADC is functional down to supply voltage of 0.5V with proper performance and minimal power consumption of 6.28nW.