RF Mixer Design for Zero IF Wi-Fi Receiver in CMOS

In this thesis work, a design of RF down-conversion mixer for WLAN standard, such as Wi-Fi or Bluetooth is presented. The target technology is 0.35um CMOS process. Several mixer topologies are analyzed and simulated at the schematic level using the Cadence Spectre-RF software. The active double balanced mixer is chosen for the ultimate implementation. For this mixer simulation results from schematic level to layout level are presented and discussed in detail. To build an RF front-end, the complete mixer is integrated with an available LNA block. The performance of the front-end is evaluated as well. The obtained simulation results satisfy the specification for Wi-Fi standard. Since the RF front-end is designed for testability, the fault simulation is incorporated as well. So the performance of the front end is also evaluated for so called “spot defects”, typical of CMOS technology. They are modeled using resistive shorts or opens in the circuit