Add to ORKGSIGLEKULeuven Campusbibliotheek Exacte Wetenschappen / UCL - Université Catholique de LouvainBEBelgiu
Abstract- This paper addresses the problem of true delay estimation during high level design. The ex...
Accurate timing information of circuits is essential for high quality designs. This paper presents a...
International audienceThis paper describes the method used in the design of a 26 million transistors...
This thesis presents systematic modeling and analysis techniques for the accurate and efficient timi...
We propose a hierarchical timing analysis technique for combinational circuits under the tightest kn...
We present a novel method to perform timing analysis of hierarchical circuits. It is based on the re...
This thesis concerns the problem of timing verification and synthesis of circuits for robust delay f...
A new and efficient procedure is proposed to evaluate the timing performance of VLSI circuits with c...
This thesis focuses on a new approach to timing and functional verification of fullcustom transistor...
The incorporation of timing makes circuit verification computationally expensive. This paper propose...
Verifying timed circuits is a complex problem even when the delays of the system are fixed. This pap...
ISBN: 978-2-84813-131-3With the technological advances in microelectronics, the traditional "fully s...
Abstract- This paper addresses the problem of true delay estimation during high level design. The ex...
Verifying timed circuits is a complex problem even when the delays of the system are fixed. This pap...
Abstract—This paper shows that the group delay of a delay circuit does not give sufficient informati...
Abstract- This paper addresses the problem of true delay estimation during high level design. The ex...
Accurate timing information of circuits is essential for high quality designs. This paper presents a...
International audienceThis paper describes the method used in the design of a 26 million transistors...
This thesis presents systematic modeling and analysis techniques for the accurate and efficient timi...
We propose a hierarchical timing analysis technique for combinational circuits under the tightest kn...
We present a novel method to perform timing analysis of hierarchical circuits. It is based on the re...
This thesis concerns the problem of timing verification and synthesis of circuits for robust delay f...
A new and efficient procedure is proposed to evaluate the timing performance of VLSI circuits with c...
This thesis focuses on a new approach to timing and functional verification of fullcustom transistor...
The incorporation of timing makes circuit verification computationally expensive. This paper propose...
Verifying timed circuits is a complex problem even when the delays of the system are fixed. This pap...
ISBN: 978-2-84813-131-3With the technological advances in microelectronics, the traditional "fully s...
Abstract- This paper addresses the problem of true delay estimation during high level design. The ex...
Verifying timed circuits is a complex problem even when the delays of the system are fixed. This pap...
Abstract—This paper shows that the group delay of a delay circuit does not give sufficient informati...
Abstract- This paper addresses the problem of true delay estimation during high level design. The ex...
Accurate timing information of circuits is essential for high quality designs. This paper presents a...
International audienceThis paper describes the method used in the design of a 26 million transistors...