THE HIERARCHICAL METHOD OF PARALLEL FORMS OF THE COMPUTING ALGORITHMS FOR THE REFLECTION TO THE MATRIX PROCESSOR WITH THE SYSTOLIC ARCHITECTURE

Developed has been a single formal method of building of the parallel forms of the computing algorithms for the reflection on the systolic processors with the digit order processing of information, the systolic processors for realization of the iteration algorithms and the systolic processors with fixed number of the processor elements. The methods of reflection of the graph representations of the multilevel computer algorithms on the multiprocessor computing devices have been offered. The methods of modification of the graphs of dependences, ensuring the building of the multilevel algorithms, adequate to architecture, corresponding to SBIS-processor at maximum degree. The parallel algorithms of solution of some problems, representing the models of the systolic matrix processors, obtained on the base of the offered methods, have been builtAvailable from VNTIC / VNTIC - Scientific & Technical Information Centre of RussiaSIGLERURussian Federatio