Chemisches-mechanisches Polieren von Si-Wafern Schlussbericht

Goal of the project was the construction, the build and the testing of a polisher for planarisation during the manufacturing of advanced integrated circuits (ICs). Together with the polishing tool manufacturer Peter Wolters Werkzeugmaschinen GmbH, Rendsburg, Germany, a new cluster tool for chemical-mechanical polishing with subsequent post-CMP cleaning including an in-line thickness measurement tool has been developed. During the concept phase Siemens worked out a profile for a CMP tool. A dry-in, dry-out concept, in-situ measurement and endpoint detection are mandatory to place the tool on the market. A cost of ownership analysis was done to identify the major cost contributors. To support the FhG-ISiT in process development an experiment was performed to evaluate the removal rate and non-uniformity of doped oxides with respect to different doping concentrations. A process simulation was done to gain a more profound understanding of the effects of process parameters on the polishing rate and uniformity. Relative velocity and back pressure were selected as input parameters for the model. With the process developed by the FhG-ISiT wafers with a 0.35 #mu#m Siemens CMOS logic product were polished at the FhG-ISiT and compared with the Siemens process as a reference. The electrical data were comparable. (orig.)Available from TIB Hannover: F97B2077+a / FIZ - Fachinformationszzentrum Karlsruhe / TIB - Technische InformationsbibliothekSIGLEBundesministerium fuer Bildung, Wissenschaft, Forschung und Technologie, Bonn (Germany)DEGerman