Synthese Digitaler Systeme (SYDIS) Schlussbericht

Remarkable features of digital systems are complexity and variety of subsystems. Computer based embedded systems gain more and more importance. In view of the necessity of a constantly reduced design time hardware software codesign will become key issue because commercially available logic and high level synthesis tools do not meet the changed and more complex requirements. Therefore the goal of this project supported by BMBF was to rationalize hardware software codesign. The following tasks have been worked on in the project: 1. PROLOG data base specifications of complex components and VHDL models of processors. In this way evaluation and validation possibilities are offered which are inevitable in hardware software codesign. 2. Development of design improvement procedures improving designs as neccessary (timing, area, throughput) by postprocessing. In this way hardware software codesign could eliminate within the design flow multiple iterations with modified control parameters the influence of which being hardly to predict. Besides, a design improvement workbench has been implemented to ease usage of commercial tools, converters, and self-developed tools. 3. Top-down hardware software codesign of a transport multiplexer from Digital Audio Broadcasting (DAB). This example of a special, practical relevant class of problems is characterized by parallel asynchronous processes. (orig.)SIGLEAvailable from TIB Hannover: DtF QN1(39,28) / FIZ - Fachinformationszzentrum Karlsruhe / TIB - Technische InformationsbibliothekBundesministerium fuer Bildung, Wissenschaft, Forschung und Technologie, Bonn (Germany)DEGerman