This thesis concentrates on nonuniform traffic patterns in one class of interconnection networks, the multistage interconnection networks (e.g. Delta and Generalized-Cube networks). Effects of static and dynamic nonuniform traffic patterns in interconnection networks are investigated, a scheme to classify networks with respect to the achievable performance is presented, and methods for performance enhancement in those networks are proposed. The performance evaluation is based on parallel network simulation running on SIMD computers. The implementation of a network simulator on a large-scale SIMD machine gives the programmer multiple choices of how to map the network structure onto the machine. A major distinction between the various mapping...
Abstract. The paper presents a platform, named Parallel Internet Traffic Simulator (PITS), which all...
Run-time reconfigurable interconnection networks can provide significant performance gains in shared...
In this paper, we propose a packet-based, off-chip, multi-processor/memory simulation framework to m...
Methods for simulating multistage interconnection networks using massively parallel SIMD computers a...
1 Methods for simulating multistage interconnection networks using massively parallel SIMD computers...
The paper describes techniques used to obtain stable high performance from parallel simulation of la...
Simulation is a tool that can be used to assess functionality and performance of communication netwo...
The principal modelling and simulation features of multistage interconnection networks operating in ...
Abstract-A formal mathematical model of single instruc-tion stream-multiple data stream (SIMD) machi...
This paper describes the parallel implementation of the TRANSIMS traffic micro-simulation. The paral...
In order to be able to develop robust and effective parallel applications and algorithms, one should...
This paper describes the parallel implementation of the TRANSIMS traffic micro-simulation. The paral...
Abstract. In recent years, requirements for performance evaluation techniques of a large-scale netwo...
Discrete event simulation is widely used within the networking community for purposes such as demon-...
Large scale simulations of Intelligent Transportation Systems (ITS) can only be achieved by using th...
Abstract. The paper presents a platform, named Parallel Internet Traffic Simulator (PITS), which all...
Run-time reconfigurable interconnection networks can provide significant performance gains in shared...
In this paper, we propose a packet-based, off-chip, multi-processor/memory simulation framework to m...
Methods for simulating multistage interconnection networks using massively parallel SIMD computers a...
1 Methods for simulating multistage interconnection networks using massively parallel SIMD computers...
The paper describes techniques used to obtain stable high performance from parallel simulation of la...
Simulation is a tool that can be used to assess functionality and performance of communication netwo...
The principal modelling and simulation features of multistage interconnection networks operating in ...
Abstract-A formal mathematical model of single instruc-tion stream-multiple data stream (SIMD) machi...
This paper describes the parallel implementation of the TRANSIMS traffic micro-simulation. The paral...
In order to be able to develop robust and effective parallel applications and algorithms, one should...
This paper describes the parallel implementation of the TRANSIMS traffic micro-simulation. The paral...
Abstract. In recent years, requirements for performance evaluation techniques of a large-scale netwo...
Discrete event simulation is widely used within the networking community for purposes such as demon-...
Large scale simulations of Intelligent Transportation Systems (ITS) can only be achieved by using th...
Abstract. The paper presents a platform, named Parallel Internet Traffic Simulator (PITS), which all...
Run-time reconfigurable interconnection networks can provide significant performance gains in shared...
In this paper, we propose a packet-based, off-chip, multi-processor/memory simulation framework to m...