Innovative Montagetechnologie fuer Qualitaetsbauelemente (INNOMONT). Teilprojekt: Techniken fuer hoehere Integrationsgrade Abschlussbericht

Within the scope of the R and D-project 'Techniques of higher integration levels' the following actions were carried out. By means of the study 'chip size package' the technologies of Chip Size Package (CSP) and 3D-assembly were researched. Different CSP-technologies, the current competitive package designs and the industry infrastructure were compiled, a market analysis and a view of cost situation were made. A second priority of the study was the investigation of the state of the art in 3D-assembly with the focus on the activities of the different semiconductor manufacturers and the used assembly techniques. As a R and D-task two CSP-demonstrators with 16 DRAM chips were assembled. The first demonstrator with #mu#BGA-technology was investigated with regard to achievable quality and reliability of the package. In this connection first risks of the #mu#BGA-technology could be seen and one of the result was, that this technology could not be transferred to all chip-designs automatically. On the second demonstrator, assembled in a new low cost CSP-technology extensive failure analysis investigations were performed. All defects, resulting from the individual process steps were identified and analysed. Measures for process improvement and optimisation were discussed. New methods of failure analysis were tested and evaluated. The research on the demonstrators give excellent experiences on processing of CSPs and the used materials in this field. (orig.)SIGLEAvailable from TIB Hannover: F98B1314+a / FIZ - Fachinformationszzentrum Karlsruhe / TIB - Technische InformationsbibliothekBundesministerium fuer Bildung, Wissenschaft, Forschung und Technologie, Bonn (Germany)DEGerman