Power minimisation techniques for testing low power VLSI circuits

Power Minimisation Techniques for Testing Low Power VLSI Circuits (PhD Dissertation)

Nicolici, N.

October 2000

Testing low power very large scale integrated (VLSI) circuits has recently become an area of concern...

Power semiconductor devices in A.C. circuit protection

Fletcher, R.

January 1987

SIGLEAvailable from British Library Document Supply Centre-DSC:DX207039 / BLDSC - British Library Do...

Low power optimization technique for BDD mapped circuits

Lindgren, Per
Kerttu, Mikael
Thornton, Mitchell
Drechsler, Rolf

January 2001

The minimization of power consumption is an important design constraint for circuits used in portabl...

Power minimisation techniques for testing low power VLSI circuits

Nicolici, N.

January 2000

SIGLEAvailable from British Library Document Supply Centre-DSC:DXN040606 / BLDSC - British Library D...

Power Minimisation Techniques for Testing Low Power VLSI Circuits

Nicolici, Nicola
Al-Hashimi, Bashir M

April 2000

Power dissipation has become a significant concern in deep submicron VLSI and a substantial amount o...

Energy minimisation techniques for distributed embedded systems

Schmitz, Marcus Thomas

January 2003

Available from British Library Document Supply Centre- DSC:DXN064858 / BLDSC - British Library Docum...

Effective Low Power Testing strategy with respect to Built in Self-Test(BIST): A Survey

Agrawal, Swati
Singh, Dharmendra Kumar

March 2018

Low-power VLSI circuits are indispensable for modern electronic devices, and numerous hardware/softw...

A survey of optimization techniques targeting low power circuits

Srinivas Devadas
Sharad Malik

January 1995

Abstract—We survey state-of-the-art optimization methods that target low power dissipation in VLSI c...

Development of low cost in-situ testing devices

Akbar, A.

January 2001

Available from British Library Document Supply Centre-DSC:DXN044322 / BLDSC - British Library Docume...

Low power CMOS circuits

Teo, Kok Chin

January 2014

Basic building block of CMOS integrated circuit like inverter, NAND, Latch and Full Adder will be si...

Low power FIR filter implementations for VLSI-based DSP systems

Erdogan, A.T.

January 1999

SIGLEAvailable from British Library Document Supply Centre-DSC:DX207707 / BLDSC - British Library Do...

Analog IC techniques for low-voltage low-power electronics

Serdijn, W.A.
Verhoeven, C.J.M.
Van Roermund, A.H.M.

December 1995

Analog IC Techniques lor Low-Voltage Low Power Electronics addresses many very important, but recent...

Labomtoire dlnformatique de Robotique et de Microilectronique de Montpellier,

Patrick Girard

December 2014

Power and energy consumption of digital systems may increase significantly during testing. This extr...

Low Power CMOS Digital Design

Anantha P. Chandrakasan
Samuel Sheng
Robert W. Brodersen

January 1995

Motivated by emerging battery operated applications that demand intensive computation in portable en...

Low power processor system study Phase 2 final report

Durrant, R.
Stevens, J
British Aerospace (Space Systems) Ltd., Bristol (United Kingdom)

January 1989

Vol. 1 of 2SIGLEAvailable from British Library Document Supply Centre- DSC:3425.929(ESA-CR-P--3142/1...

Power Minimisation Techniques for Testing Low Power VLSI Circuits (PhD Dissertation)

Nicolici, N.

October 2000

Testing low power very large scale integrated (VLSI) circuits has recently become an area of concern...

Power semiconductor devices in A.C. circuit protection

Fletcher, R.

January 1987

SIGLEAvailable from British Library Document Supply Centre-DSC:DX207039 / BLDSC - British Library Do...

Low power optimization technique for BDD mapped circuits

Lindgren, Per
Kerttu, Mikael
Thornton, Mitchell
Drechsler, Rolf

January 2001

The minimization of power consumption is an important design constraint for circuits used in portabl...

Power minimisation techniques for testing low power VLSI circuits

Nicolici, N.

January 2000

SIGLEAvailable from British Library Document Supply Centre-DSC:DXN040606 / BLDSC - British Library D...

Power Minimisation Techniques for Testing Low Power VLSI Circuits

Nicolici, Nicola
Al-Hashimi, Bashir M

April 2000

Power dissipation has become a significant concern in deep submicron VLSI and a substantial amount o...

Energy minimisation techniques for distributed embedded systems

Schmitz, Marcus Thomas

January 2003

Available from British Library Document Supply Centre- DSC:DXN064858 / BLDSC - British Library Docum...

Effective Low Power Testing strategy with respect to Built in Self-Test(BIST): A Survey

Agrawal, Swati
Singh, Dharmendra Kumar

March 2018

Low-power VLSI circuits are indispensable for modern electronic devices, and numerous hardware/softw...

A survey of optimization techniques targeting low power circuits

Srinivas Devadas
Sharad Malik

January 1995

Abstract—We survey state-of-the-art optimization methods that target low power dissipation in VLSI c...

Development of low cost in-situ testing devices

Akbar, A.

January 2001

Available from British Library Document Supply Centre-DSC:DXN044322 / BLDSC - British Library Docume...

Low power CMOS circuits

Teo, Kok Chin

January 2014

Basic building block of CMOS integrated circuit like inverter, NAND, Latch and Full Adder will be si...

Low power FIR filter implementations for VLSI-based DSP systems

Erdogan, A.T.

January 1999

SIGLEAvailable from British Library Document Supply Centre-DSC:DX207707 / BLDSC - British Library Do...

Analog IC techniques for low-voltage low-power electronics

Serdijn, W.A.
Verhoeven, C.J.M.
Van Roermund, A.H.M.

December 1995

Analog IC Techniques lor Low-Voltage Low Power Electronics addresses many very important, but recent...

Labomtoire dlnformatique de Robotique et de Microilectronique de Montpellier,

Patrick Girard

December 2014

Power and energy consumption of digital systems may increase significantly during testing. This extr...

Low Power CMOS Digital Design

Anantha P. Chandrakasan
Samuel Sheng
Robert W. Brodersen

January 1995

Motivated by emerging battery operated applications that demand intensive computation in portable en...

Low power processor system study Phase 2 final report

Durrant, R.
Stevens, J
British Aerospace (Space Systems) Ltd., Bristol (United Kingdom)

January 1989

Vol. 1 of 2SIGLEAvailable from British Library Document Supply Centre- DSC:3425.929(ESA-CR-P--3142/1...

Power Minimisation Techniques for Testing Low Power VLSI Circuits (PhD Dissertation)

Nicolici, N.

October 2000

Testing low power very large scale integrated (VLSI) circuits has recently become an area of concern...

Power semiconductor devices in A.C. circuit protection

Fletcher, R.

January 1987

SIGLEAvailable from British Library Document Supply Centre-DSC:DX207039 / BLDSC - British Library Do...

Low power optimization technique for BDD mapped circuits

Lindgren, Per
Kerttu, Mikael
Thornton, Mitchell
Drechsler, Rolf

January 2001

The minimization of power consumption is an important design constraint for circuits used in portabl...

Power minimisation techniques for testing low power VLSI circuits

Abstract

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Power minimisation techniques for testing low power VLSI circuits

Abstract

Extracted data

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