Hardware architectures for high-performance image and video processing

This PhD work has resulted in the development of a set of novel architectures and algorithms for high-performance image and video processing applications. The main architecture contributions are: 1) A range of area-efficient novel 3D median filter architectures for real time 3D noise removal. The proposed 3D median filter can be applied for both video and 3D medical images. Separately, one of the filter implementations on an FPGA was applied to processing the output from a low-light digital video camera (by Andor Technologies), as a demonstration of a typical scenario where this form of real time filtering is particularly applicable. 2) An area-efficient real time 3D wavelet transform processor architecture. The synthesis results show that the proposed 5-stage bit-parallel OA architecture can perform the 3D Wavelet transform on typical fMRI data at several volumes per second on a single FPGA. Implementation on a larger, more recent FPGA would provide real time performance. 3) A novel Full Search Block Matching (FSBM) architecture which maps the partial distortion elimination algorithm (POE) into a parallel systolic array processor with an Early-Jump-Out (EJO) / Early-Tum-Off (ETO) control unit. RTL simulation indicates that the proposed low power architecture could in some cases save about 50% of the power consumption for this part of motion estimation in MPEG-2/4 and H.264 video compression. 4) A generic image feature matching hardware engine on FPGAs for fast feature-based image retrieval, illustrated by an architecture with an Earlier-Jump-Out (EJO) control unit for fingerprint matching at potentially 1.23 million fingerprints per second. This architectural framework could be adapted for feature matching-based retrieval using other features and distance measures. 5) A novel low power, high radix multiplication architecture. Performance tests based on the number of bit reversals indicate that the power consumption estimated by this measure can be reduced by around 50% in comparison with the conventional multiplier. Although these application-specific circuit architectures are disparate with different characteristics and techniques, there are several reusable techniques which we have developed in the process which can be used for other hardware architectures: 1) The Early-Jump-Out (or Early-Tum-Off) approach applied in motion estimation and fingerprint matching can be generalized for many other multimedia search and image database retrieval applications. The primary purpose of the ETO form is to save power when certain elements of a regUlar array computation can be terminated early. The more standard EJO form can be used to speed up a more asynchronous (serial) search process. 2) The Proposed low-power high-radix BSO multiplication architecture, as a basic module for digital circuit design, can be applied in a wide range of circuit applications; The project also developed a novel facet-based Bayesian approach for video object motion tracking, which has been tested with a number of video clips. This approach can be also applied for high-level video retrieval as well as the basis of further hardware-based VO tracking. Based on the above work, 5 journal papers and 4 conference papers have been pUblished, and other 3 papers are under review. A patent for the BSO Multiplier has been applied for.EThOS - Electronic Theses Online ServiceGBUnited Kingdo