Hard-wiring interval arithmetic

Floating point arithmetic has become prevalent in virtually every scientific computation, yet suffers from rounding, truncation and catastrophic cancellation errors to the extent that the result may be completely inaccurate. Whilst modern processors do not have the capabilities to natively support interval arithmetic, it can be implemented in software though such a method of implementation results in larger program size and often more than doubles execution times. Embedded systems do not have the luxury of utilising software implementations of interval arithmetic and so a hardware based alternative must be sought. This thesis examines the algorithms traditionally used for interval multiplication and proposes a new method, free of the caveats which plague traditional multiplication computation. The inherent parallelism of these algorithms is examined to determine their throughput and latency characteristics, given a selection of platforms which exhibit variations in the number of input buses, FPUs and result buses. A software implementation of each method of interval multiplication is described, alongside their relative performances. Given the data-dependant nature of interval computation and the current trend towards vector processing architectures, these software implementations include reformulations of both tradi- tional methods of interval multiplication to provide vectorisation of the software and thus completely eliminate branching. Realised as co-processors to the Altera Nios Il, this thesis describes the design decisions, specification, area requirements, power utilisation and per-cycle performance of hardware implementations of the brute-force, nine case and herein presented integer-based interval multipliers.EThOS - Electronic Theses Online ServiceGBUnited Kingdo