Add to ORKGThis communication presents the evidence of a degradation effect causing important reductions in the delay of a CMOS inverter when consecutive input transition are close in time. Complete understanding of the effect is demonstrated, providing a quantifying model. Fully characterization as a function of design variables and external conditions is carried out, making the model suitable for using in library characterization as well as simulation at a transistor level. Comparison with HSPICE level 6 simulations shows satisfactory accuracy for timing evaluation.Comisión Interministerial de Ciencia y Tecnología TIC 95-009
AbstractPropagation delay is one of the important issues for designing and synthesizing any VLSI cir...
This communication presents HALOTIS, a novel high accuracy logic timing simulation tool, that incor...
Soft errors can occur in digital integrated circuits (ICs) as a result of an electromagnetic disturb...
The authors present the Inertial and Degradation Delay Model (IDDM) for CMOS digital simulation. Th...
International audienceDelay estimation is a crucial task in digital circuit design as it provides th...
Timing verification of digital CMOS circuits is a key point in the design process. In this contribu...
12th International Workshop, PATMOS: : International Workshop on Power and Timing Modeling, Optimiza...
Based on an explicit formulation of delays, an improved model for low voltage operation of CMOS inve...
As delay models used in logic timing simulation become more and more complex, the problem of model ...
In this paper an accurate, analytical model for the evaluation of the CMOS inverter delay in the sub...
Due to the continual development of the CMOS IC technology, there is a corresponding strong demand f...
An accurate and fast technique has been developed for computing the supply current as well as the de...
An improved timing model for CMOS combinational logic is presented. The model is based on an analyti...
International audienceFast digital timing simulations based on continuous-time, digital-value circui...
An alternative switching delay reduction technique for CMOS & BiCMOS digital circuits is examined. A...
AbstractPropagation delay is one of the important issues for designing and synthesizing any VLSI cir...
This communication presents HALOTIS, a novel high accuracy logic timing simulation tool, that incor...
Soft errors can occur in digital integrated circuits (ICs) as a result of an electromagnetic disturb...
The authors present the Inertial and Degradation Delay Model (IDDM) for CMOS digital simulation. Th...
International audienceDelay estimation is a crucial task in digital circuit design as it provides th...
Timing verification of digital CMOS circuits is a key point in the design process. In this contribu...
12th International Workshop, PATMOS: : International Workshop on Power and Timing Modeling, Optimiza...
Based on an explicit formulation of delays, an improved model for low voltage operation of CMOS inve...
As delay models used in logic timing simulation become more and more complex, the problem of model ...
In this paper an accurate, analytical model for the evaluation of the CMOS inverter delay in the sub...
Due to the continual development of the CMOS IC technology, there is a corresponding strong demand f...
An accurate and fast technique has been developed for computing the supply current as well as the de...
An improved timing model for CMOS combinational logic is presented. The model is based on an analyti...
International audienceFast digital timing simulations based on continuous-time, digital-value circui...
An alternative switching delay reduction technique for CMOS & BiCMOS digital circuits is examined. A...
AbstractPropagation delay is one of the important issues for designing and synthesizing any VLSI cir...
This communication presents HALOTIS, a novel high accuracy logic timing simulation tool, that incor...
Soft errors can occur in digital integrated circuits (ICs) as a result of an electromagnetic disturb...