Online Thread and Data Mapping Using a Sharing-Aware Memory Management Unit

  • Cruz, Eduardo,
  • Diener, Matthias
  • Lima Pilla, Laércio
  • Navaux, Philippe,
Publication date
January 2021
Publisher
Association for Computing Machinery (ACM)

Abstract

International audienceCurrent and future architectures rely on thread-level parallelism to sustain performance growth. These architectures have introduced a complex memory hierarchy, consisting of several cores organized hierarchically with multiple cache levels and NUMA nodes. These memory hierarchies can have an impact on the performance and energy efficiency of parallel applications as the importance of memory access locality is increased. In order to improve locality, the analysis of the memory access behavior of parallel applications is critical for mapping threads and data. Nevertheless, most previous work relies on indirect information about the memory accesses, or does not combine thread and data mapping, resulting in less accurate ...

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