International audiencePower gating is an efficient technique for reducing leakage power by disconnecting idle blocks from power supply. Gated blocks cause changes in current densities on the grid. Even in DC conditions for some power gating configuration (PGC), current densities in some branches may increase to the extent of violating electromigration (EM) constraints. The existing DC methods optimize the grid under voltage drop (IR) and EM constraints for a single configuration of blocks. We analyze the effects of power gating and develop a grid sizing algorithm to satisfy all reliability constraints for multiple PGCs with only a small increase in area
Power has become an important design closure parameter in today’s ultra low submicron digital design...
International audienceA recently proposed methodology for electromigration (EM) assessment in on-chi...
Electromigration (EMG) is a consequence of miniaturization of integrated circuits in general and the...
International audiencePower gating is an efficient technique for reducing leakage power in electroni...
International audienceWe present a reliability study of power grids in power-gated chips. We investi...
A major challenge in modern chip design is the design and analysis of the chip's power grid -- the n...
As technology scales into smaller feature sizes, electromigration (EM) has become a progressively se...
Power grid voltage integrity verification requires checking if all the voltage drops on the grid ar...
[[abstract]]System-on-a-chip with multiple power domains reduces leakage power consumption by power ...
Power integrity has become a critical issue in nano-scale VLSI design. With technology scaling, the ...
\u3cp\u3ePower gating (PG) has emerged as an effective technique to reduce standby leakage power in ...
Row-based power-gating has recently emerged as a meet-in-the-middle sleep transistor insertion parad...
Verifying the power grid requires checking if the voltage drops on all the nodes do not exceed the t...
Row-based power-gating has recently emerged as a meet-in-the-middle sleep transistor insertion parad...
Abstract — Power gating is widely accepted as an efficient way to suppress subthreshold leakage curr...
Power has become an important design closure parameter in today’s ultra low submicron digital design...
International audienceA recently proposed methodology for electromigration (EM) assessment in on-chi...
Electromigration (EMG) is a consequence of miniaturization of integrated circuits in general and the...
International audiencePower gating is an efficient technique for reducing leakage power in electroni...
International audienceWe present a reliability study of power grids in power-gated chips. We investi...
A major challenge in modern chip design is the design and analysis of the chip's power grid -- the n...
As technology scales into smaller feature sizes, electromigration (EM) has become a progressively se...
Power grid voltage integrity verification requires checking if all the voltage drops on the grid ar...
[[abstract]]System-on-a-chip with multiple power domains reduces leakage power consumption by power ...
Power integrity has become a critical issue in nano-scale VLSI design. With technology scaling, the ...
\u3cp\u3ePower gating (PG) has emerged as an effective technique to reduce standby leakage power in ...
Row-based power-gating has recently emerged as a meet-in-the-middle sleep transistor insertion parad...
Verifying the power grid requires checking if the voltage drops on all the nodes do not exceed the t...
Row-based power-gating has recently emerged as a meet-in-the-middle sleep transistor insertion parad...
Abstract — Power gating is widely accepted as an efficient way to suppress subthreshold leakage curr...
Power has become an important design closure parameter in today’s ultra low submicron digital design...
International audienceA recently proposed methodology for electromigration (EM) assessment in on-chi...
Electromigration (EMG) is a consequence of miniaturization of integrated circuits in general and the...