8x8 Multiplier Based on Adiabatic Static Logic

This paper continues presenting measurement results of a larger digital system based on the adiabatic static logic (ASL). The fundamental purpose of the research have been too investigate the useability of the ASL gates on a larger system as a possible solution to the power consumption problem existing in many digital CMOS circuits; an additional purpose of the present study have been to prove that a double clocked power source increases the power efficiency of the ASL system over the sigle clocked version. This time, a 8x8 multiplier was used as a demonstration