Digital design of a one megabit magneto-resistive memory incorporating efficient hardware fault tolerance

The research documented in this thesis was undertaken to improve and advance magneto-resistive (MR) memory design. This new memory technology shows great promise in many areas of modern computer systems;Our research team completed a design and partial layout of the first MR memory to operate in the voltage mode. This thesis focuses on the related areas of architecture and hardware fault tolerance. In the area of architecture, an overall chip organization was developed. Compact and space efficient layouts of MR cells and supporting circuitry also were designed. In the area of hardware fault tolerance, various techniques for improving chip yield and reliability in the presence of hardware failures, by means of, spares and error-correcting and detecting logic, were investigated and reported;Chapter 1 introduces computer memory systems and emphasizes the key advantages of MR memories over existing memory technologies. Chapter 2 provides information about the historical and theoretical background of MR memories. Chapter 3 provides an overview of the 1-megabit chip, in a top-down format, and provides a foundation on which the remaining more detailed chapters will be built. Chapter 4 contains details of the sense line design, and Chapter 5 discusses the details of support logic. Chapter 6 discusses yield-enhancing techniques, and Chapter 7 contains concluding remarks