This work proposes in-situ Real-Time Error Detection (RTD): embedding hardware in a memory array for detecting a fault in the array when it occurs, rather than when it is read. RTD breaks the serialization between data access and error detection and, thus, it can speed-up the access-time of arrays that use in-line error-detection and correction. The approach can also reduce the time needed to root-cause array related bugs during post-silicon validation and product testing. The paper presents how to build RTD into an array with flip-flops to track in real-time the column-parity and introduces a two-dimensional RTD based error-correction scheme. As compared to SECDED, the evaluated scheme has comparable error-detection and correction strength...
The key objective of database systems is to reliably manage data, whereby high query throughput and ...
This paper presents iRazor, a lightweight error detection and correction approach, to suppress the c...
This paper deals with on-line error detection in digital circuits implemented in FPGAs. Error detect...
This work proposes an SRAM array with built-in real-time error detection (RTD) capabilities. Each ce...
112 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1993.Processor arrays can provide ...
This paper describes a methodology based on dependency graphs for doing concurrent runtime error det...
In this paper, we present a hardware technique, called Self-Repairing Array Structures (SRAS), for m...
Data that is either transmitted over communication channel (e.g.bus) or stored in memory is not comp...
Local triple modular redundancy (LTMR) is often the first choice to harden a flash-based FPGA applic...
Errors introduced by radiation-induced single event upset and single event latchup in very deep subm...
Previous software-only error detection techniques have provided high-coverage, low-latency detection...
Local triple modular redundancy (LTMR) is often the first choice to harden the FFs of a flash-based ...
System reliability is becoming a significant concern as technology continues to shrink. This is beca...
We propose a low cost concurrent error detection strategy to improve the Reliability, Availability, ...
We propose a low cost concurrent error detection strategy to improve the Reliability, Availability, ...
The key objective of database systems is to reliably manage data, whereby high query throughput and ...
This paper presents iRazor, a lightweight error detection and correction approach, to suppress the c...
This paper deals with on-line error detection in digital circuits implemented in FPGAs. Error detect...
This work proposes an SRAM array with built-in real-time error detection (RTD) capabilities. Each ce...
112 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1993.Processor arrays can provide ...
This paper describes a methodology based on dependency graphs for doing concurrent runtime error det...
In this paper, we present a hardware technique, called Self-Repairing Array Structures (SRAS), for m...
Data that is either transmitted over communication channel (e.g.bus) or stored in memory is not comp...
Local triple modular redundancy (LTMR) is often the first choice to harden a flash-based FPGA applic...
Errors introduced by radiation-induced single event upset and single event latchup in very deep subm...
Previous software-only error detection techniques have provided high-coverage, low-latency detection...
Local triple modular redundancy (LTMR) is often the first choice to harden the FFs of a flash-based ...
System reliability is becoming a significant concern as technology continues to shrink. This is beca...
We propose a low cost concurrent error detection strategy to improve the Reliability, Availability, ...
We propose a low cost concurrent error detection strategy to improve the Reliability, Availability, ...
The key objective of database systems is to reliably manage data, whereby high query throughput and ...
This paper presents iRazor, a lightweight error detection and correction approach, to suppress the c...
This paper deals with on-line error detection in digital circuits implemented in FPGAs. Error detect...