We present a high-throughput FPGA design for supporting high-performance network switching. FPGAs have recently been attracting attention for datacenter computing due to their increasing transceiver count and capabilities, which also benefit the implementation and refinement of network switches. Our solution replaces the crossbar in favour of a novel, more pipeline-friendly approach, the “Combined parallel round-robin arbiter”. It also removes the overhead of incorporating an often-iterative scheduling or matching algorithm, which sometimes tries to fit too many steps in a single or a few FPGA cycles. The result is a network switch implementation on FPGAs operating at a high frequency and with a low port-to-port latency. It also provides a ...
This research investigates packet switching with gigabit-per-second ports for integrated broadband s...
This research investigates packet switching with gigabit-per-second ports for integrated broadband s...
AbstractThe use of on chip networks as interconnection media for systems implemented in FPGAs is lim...
We present Hipernetch, a novel FPGA-based design for performing high-bandwidth network switching. FP...
This paper presents a novel FPGA-based switch design that achieves high algorithmic performance and ...
FPGAs are being increasingly used on networkinterface cards (NICs) as offload units to accelerate pa...
Communications systems make heavy use of FPGAs; their programmability allows system designers to kee...
High-performance routers have the task of transmitting traffic in between the nodes of the Internet,...
Network routers rely on an important hardware component, namely the switch fabric, responsible for f...
Network routers rely on an important hardware component, namely the switch fabric, responsible for f...
Packet switches are used in the Internet to forward information between a sender and receiver and ar...
Packet switches are used in the Internet to forward information between a sender and receiver and ar...
As we entered the new millennium, we swiftly moved from an industrial economy into an information ec...
This thesis work proposes ReFlex Switch, a novel, scalable on-chip packet switch architecture, that...
In this paper, we introduce a Roundrobin Arbiter Generator (RAG) tool. The RAG tool can generate a...
This research investigates packet switching with gigabit-per-second ports for integrated broadband s...
This research investigates packet switching with gigabit-per-second ports for integrated broadband s...
AbstractThe use of on chip networks as interconnection media for systems implemented in FPGAs is lim...
We present Hipernetch, a novel FPGA-based design for performing high-bandwidth network switching. FP...
This paper presents a novel FPGA-based switch design that achieves high algorithmic performance and ...
FPGAs are being increasingly used on networkinterface cards (NICs) as offload units to accelerate pa...
Communications systems make heavy use of FPGAs; their programmability allows system designers to kee...
High-performance routers have the task of transmitting traffic in between the nodes of the Internet,...
Network routers rely on an important hardware component, namely the switch fabric, responsible for f...
Network routers rely on an important hardware component, namely the switch fabric, responsible for f...
Packet switches are used in the Internet to forward information between a sender and receiver and ar...
Packet switches are used in the Internet to forward information between a sender and receiver and ar...
As we entered the new millennium, we swiftly moved from an industrial economy into an information ec...
This thesis work proposes ReFlex Switch, a novel, scalable on-chip packet switch architecture, that...
In this paper, we introduce a Roundrobin Arbiter Generator (RAG) tool. The RAG tool can generate a...
This research investigates packet switching with gigabit-per-second ports for integrated broadband s...
This research investigates packet switching with gigabit-per-second ports for integrated broadband s...
AbstractThe use of on chip networks as interconnection media for systems implemented in FPGAs is lim...