In this paper we present a reliability simulation framework from atomistic simulations up to circuit simulations, including traps interactions with variability sources. Trapping and detrapping dynamics are reproduced by a kinetic Monte-Carlo engine, which enables oxide degradation simulations such as BTI and RTN phenomenon on large ensembles of atomistic devices. Based on these results compact models are extracted and circuit lifetime projections are derived. © 2013 IEEE.Link_to_subscribed_fulltex
A comprehensive simulation methodology for the systematic study of gate leakage variability in reali...
Charge trapping at the channel interface is a fundamental issue that adversely affects the reliabili...
The continuous demand for high performance applications and simultaneous lowering of power consumpti...
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The introduction of High-κ Metal Gate transistors led to higher integration density, low leakage cur...
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Current and future semiconductor technology nodes, bring about a variety of challenges that pertain ...
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Current and future semiconductor technology nodes, bring about a variety of challenges that pertain ...
This thesis presents a new technique for simulating integrated circuits, called probabilistic simula...
University of Minnesota Ph.D. dissertation. October 2012. Major: Electrical Engineering. Advisor: Sa...
This paper discusses an efficient method to analyze the spatial and temporal reliability of analog a...
Degradation behaviors in the high-k/metal gate stacks of nMOSFETs are investigated by three-dimensio...
A comprehensive simulation methodology for the systematic study of gate leakage variability in reali...
Charge trapping at the channel interface is a fundamental issue that adversely affects the reliabili...
The continuous demand for high performance applications and simultaneous lowering of power consumpti...
A blueprint for an atomistic approach to introducing time-dependent variability into a circuit simul...
The introduction of High-κ Metal Gate transistors led to higher integration density, low leakage cur...
This paper presents a thorough numerical investigation of statistical effects associated with charge...
This paper presents an extensive study of the interplay between as-fabricated (time-zero) variabilit...
Simulations of an inverter and a 32-bit SRAM bit slice are performed based on an atomistic approach....
Current and future semiconductor technology nodes, bring about a variety of challenges that pertain ...
Abstract—Aggressive scaling to nanometer CMOS technologies causes both analog and digital circuit pa...
Current and future semiconductor technology nodes, bring about a variety of challenges that pertain ...
This thesis presents a new technique for simulating integrated circuits, called probabilistic simula...
University of Minnesota Ph.D. dissertation. October 2012. Major: Electrical Engineering. Advisor: Sa...
This paper discusses an efficient method to analyze the spatial and temporal reliability of analog a...
Degradation behaviors in the high-k/metal gate stacks of nMOSFETs are investigated by three-dimensio...
A comprehensive simulation methodology for the systematic study of gate leakage variability in reali...
Charge trapping at the channel interface is a fundamental issue that adversely affects the reliabili...
The continuous demand for high performance applications and simultaneous lowering of power consumpti...