Nanoassembly and packaging of single carbon nanotube based transistors

Carbon nanotube transistor with bottom gate fabricated by atomic force microscopy based nanomanipulation system is presented in this paper. This process consists of fabrication of transistor chips using conventional optical lithography and nanoassembly of CNTs on the chips. It is found that the contact resistance between the CNT and Palladium electrodes can be as low as several hundred kΩ. By using this fabrication technique, high fabrication yield of CNT devices can be achieved. In addition, Polyimide serves as the dielectric layer and the packaging material of the transistor which allows us to modify transistor characteristic, because the Fermi level of CNTs shifted after annealing under vacuum. At low temperature, the polyimide has lower gas permeability and thereby, seals the CNT transistors. © 2006 IEEE.Link_to_subscribed_fulltex