Add to ORKGA novel VLSI message switch design for application in highly parallel architectures is presented. The prominent features of this design are message combining, a shared central queue structure with a dynamic boundary and nonpreemptive priority, and a look-ahead protocol between switch nodes in adjacent stages. These features alleviate memory contention and increase the effective network bandwidth.link_to_subscribed_fulltex
Current technology trends make it possible to build communication networks that can support highperf...
This paper describes an efficient mechanism of inter-processor message transfer on loosely-coupled/m...
Previous researchers in user-level message-passing parallel computing have attempted to reduce commu...
[[abstract]]© 1989 Institute of Electrical and Electronics Engineers-A novel VLSI message switch des...
In highly parallel message routing networks, it is sometimes desirable to concentrate relatively few...
[[abstract]]A switch queue structure for one-network parallel processor systems minimizes chip count...
The design of a large, multistage interconnection network that has been successfully constructed and...
Telecommunication switches have been implemented based mainly on centralized and distributed control...
Predictive multiplexed switching is a new approach for building interconnection switches for high pe...
This report describes the combining switch that we have implemented for use in the 16 \Theta 16 proc...
A simple distributed, modular architecture for a very large scale ATM switch is proposed in this pap...
[[abstract]]© 1990 Institute of Electrical and Electronics Engineers-The design of a large, multista...
A message transport mechanism which provides highbandwidth low-latency interprocessor communication ...
Multidestination message passing has been proposed as an attractive mechanism for efficiently implem...
A packet switch with parallel switching planes is a parallel packet switch (PPS). A PPS can scale-up...
Current technology trends make it possible to build communication networks that can support highperf...
This paper describes an efficient mechanism of inter-processor message transfer on loosely-coupled/m...
Previous researchers in user-level message-passing parallel computing have attempted to reduce commu...
[[abstract]]© 1989 Institute of Electrical and Electronics Engineers-A novel VLSI message switch des...
In highly parallel message routing networks, it is sometimes desirable to concentrate relatively few...
[[abstract]]A switch queue structure for one-network parallel processor systems minimizes chip count...
The design of a large, multistage interconnection network that has been successfully constructed and...
Telecommunication switches have been implemented based mainly on centralized and distributed control...
Predictive multiplexed switching is a new approach for building interconnection switches for high pe...
This report describes the combining switch that we have implemented for use in the 16 \Theta 16 proc...
A simple distributed, modular architecture for a very large scale ATM switch is proposed in this pap...
[[abstract]]© 1990 Institute of Electrical and Electronics Engineers-The design of a large, multista...
A message transport mechanism which provides highbandwidth low-latency interprocessor communication ...
Multidestination message passing has been proposed as an attractive mechanism for efficiently implem...
A packet switch with parallel switching planes is a parallel packet switch (PPS). A PPS can scale-up...
Current technology trends make it possible to build communication networks that can support highperf...
This paper describes an efficient mechanism of inter-processor message transfer on loosely-coupled/m...
Previous researchers in user-level message-passing parallel computing have attempted to reduce commu...