A new formulation for the design of FIR filters with reduced hardware implementation complexity

In this paper, we consider the design of finite-impulse response (FIR) filters, where the coefficients are expressed as sums of signed powers-of-two (SPT) terms. To consume less energy, the hardware implementation complexity is required to be reduced. That is, we need to minimize the number of SPT terms, subject to a given performance requirement This can be formulated as an integer programming problem and can be transformed into a simplified one with a conversion method, where the number of the variables is reduced. Then, an efficient algorithm based on discrete steepest descent algorithm is developed for solving this problem. For illustration, two numerical examples are solved. © 2010 IEEE.link_to_subscribed_fulltex