An Optical Lithography Method Is Disclosed That Uses Double Exposure Of A Reusable Template Mask And A Trim Mask To Fabricate Regularly-Placed Rectangular Contacts In Standard Cells Of Application-Specific Integrated Circuits (Asics). A First Exposure Of The Reusable Template Mask With Periodic Patterns Forms Periodic Dark Lines On A Wafer And A Second Exposure Of An Application-Specific Trim Mask Remove The Unwanted Part Of The Dark Lines And The Small Cuts Of The Dark Lines Left Form The Rectangular Regularly-Placed Contacts. All Contacts Are Placed Regularly In One Direction While Unrestrictedly In The Perpendicular Direction. The Regular Placement Of Patterns On The Template Mask Enable More Effective Use Of Resolution Enhancement Techn...
According to Moore\u27s law, the IC (Integrated Circuit) minimum feature size is to shrink node over...
As minimum feature sizes continue to shrink, patterned fea-tures have become significantly smaller t...
3D and Through-Silicon Vias (TSV) simplify and speed-up the chip-to-chip communication. The usage wi...
An optical lithography method is disclosed that uses double exposure of a reusable template mask and...
An optical lithography method is disclosed that uses double exposure of a reusable a chromeless alte...
A Method For Reducing Lens Aberrations Sensitivity And Proximity Effects Of Alternating Phase Shifte...
The foundation of semiconductor industry has historically been driven by scaling. Device size reduct...
As minimum feature sizes continue to shrink, patterned features have become significantly smaller th...
Moore's law has been guiding the semiconductor industry for four decades. Lithography is the ke...
The impact of grid-placed contacts on application-specific integrated circuit (ASIC) performance is ...
The practicability and methodology of applying resolution-enhancement- technique-driven regularly pl...
Optical double patterning allows for increased quality control over varying film stacks as well as a...
In this paper I present the impact of sub-wavelength optical lithography for new EDA tools, IC Layou...
The practicability and methodology of applying regularly placed contacts on layout design of standar...
According to Moore\u27s law, the IC (Integrated Circuit) minimum feature size is to shrink node over...
According to Moore\u27s law, the IC (Integrated Circuit) minimum feature size is to shrink node over...
As minimum feature sizes continue to shrink, patterned fea-tures have become significantly smaller t...
3D and Through-Silicon Vias (TSV) simplify and speed-up the chip-to-chip communication. The usage wi...
An optical lithography method is disclosed that uses double exposure of a reusable template mask and...
An optical lithography method is disclosed that uses double exposure of a reusable a chromeless alte...
A Method For Reducing Lens Aberrations Sensitivity And Proximity Effects Of Alternating Phase Shifte...
The foundation of semiconductor industry has historically been driven by scaling. Device size reduct...
As minimum feature sizes continue to shrink, patterned features have become significantly smaller th...
Moore's law has been guiding the semiconductor industry for four decades. Lithography is the ke...
The impact of grid-placed contacts on application-specific integrated circuit (ASIC) performance is ...
The practicability and methodology of applying resolution-enhancement- technique-driven regularly pl...
Optical double patterning allows for increased quality control over varying film stacks as well as a...
In this paper I present the impact of sub-wavelength optical lithography for new EDA tools, IC Layou...
The practicability and methodology of applying regularly placed contacts on layout design of standar...
According to Moore\u27s law, the IC (Integrated Circuit) minimum feature size is to shrink node over...
According to Moore\u27s law, the IC (Integrated Circuit) minimum feature size is to shrink node over...
As minimum feature sizes continue to shrink, patterned fea-tures have become significantly smaller t...
3D and Through-Silicon Vias (TSV) simplify and speed-up the chip-to-chip communication. The usage wi...