Dynamic power reduction of FPGA-based reconfigurable computers using precomputation

This paper examines the effectiveness of employing pre-computation techniques to reduce power consumption of field configurable computing systems. Multiplier is modified with pre-computation techniques and are implemented using commercial off-the-shelf FPGAs. Pre-computation techniques reduce dynamic power consumption of a module by eliminating unnecessary signal switching activities in inactive portions of the modules. Experiments have shown that up to 52% of logic and signal power consumption can be reduced in multiplier module. Furthermore, when compared to ASIC implementations, FPGA implementations of pre-computation modules have the advantage of lower area overhead as most of them can be implemented using originally unoccupied related FPGA resources. Finally, it was found that the effectiveness of pre-computation depends heavily on the input data statistics. It is expected that compilers for future reconfigurable computers may take full advantage of such power saving techniques by optimizing the architecture according to data input statistics.postprintThe 1st International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies (HEART), Tsukuba, Japan, 1 June 2010. In ACM SIGARCH Computer Architecture News, 2010, v. 38 n. 4, p. 87-9