Level-set based inverse lithography technology (ILT) treats photomask design for microlithography as an inverse mathematical problem, interpreted with a time-dependent model, and then solved as a partial differential equation with finite difference schemes. This paper focuses on developing level-set based ILT for partially coherent systems, and upon that an expectation-orient optimization framework weighting the cost function by random process condition variables. These include defocus and aberration to enhance robustness of layout patterns against process variations. Results demonstrating the benefits of defocus-aberration-aware level-set based ILT are presented. © 2011 Optical Society of America.published_or_final_versio
In the first implimentation by Luminescent of ILT-enabled Source-Mask Optimization (SMO), an ILT-opt...
We propose an alternating direction method of multipliers (ADMM) to solve an optimization problem st...
The continual shrinkage of minimum feature size in inte-grated circuit (IC) fabrication incurs more ...
Inverse lithography technology (ILT) treats photomask design for microlithography as an inverse math...
Optical proximity correction (OPC) is one of the most widely used Resolution Enhancement Techniques ...
As the feature size of integrated circuits continues to decrease, optical proximity correction (OPC)...
Optical lithography has enabled the printing of progressively smaller circuit patterns over the year...
Inverse lithography technology formulates the photomask synthesis as an inverse mathematical problem...
The lithographic performance of a photomask is sensitive to shape uncertainty caused by manufacturin...
As the feature size of integrated circuits continues to decrease, optical proximity correction (OPC)...
For semiconductor manufacturers moving toward advanced technology nodes –32nm, 22nm and below – lith...
Abstract—An efficient algorithm based on the pixel-based mask representation is proposed for fast sy...
University of Minnesota Ph.D. dissertation. August 2009. Major: Mathematics. Advisor: Fadil Santosa....
Optical lithography is a critical step in the semiconductor manufacturing process, and one key probl...
IEEE International Conference on Image ProcessingThe continual shrinkage of minimum feature size in ...
In the first implimentation by Luminescent of ILT-enabled Source-Mask Optimization (SMO), an ILT-opt...
We propose an alternating direction method of multipliers (ADMM) to solve an optimization problem st...
The continual shrinkage of minimum feature size in inte-grated circuit (IC) fabrication incurs more ...
Inverse lithography technology (ILT) treats photomask design for microlithography as an inverse math...
Optical proximity correction (OPC) is one of the most widely used Resolution Enhancement Techniques ...
As the feature size of integrated circuits continues to decrease, optical proximity correction (OPC)...
Optical lithography has enabled the printing of progressively smaller circuit patterns over the year...
Inverse lithography technology formulates the photomask synthesis as an inverse mathematical problem...
The lithographic performance of a photomask is sensitive to shape uncertainty caused by manufacturin...
As the feature size of integrated circuits continues to decrease, optical proximity correction (OPC)...
For semiconductor manufacturers moving toward advanced technology nodes –32nm, 22nm and below – lith...
Abstract—An efficient algorithm based on the pixel-based mask representation is proposed for fast sy...
University of Minnesota Ph.D. dissertation. August 2009. Major: Mathematics. Advisor: Fadil Santosa....
Optical lithography is a critical step in the semiconductor manufacturing process, and one key probl...
IEEE International Conference on Image ProcessingThe continual shrinkage of minimum feature size in ...
In the first implimentation by Luminescent of ILT-enabled Source-Mask Optimization (SMO), an ILT-opt...
We propose an alternating direction method of multipliers (ADMM) to solve an optimization problem st...
The continual shrinkage of minimum feature size in inte-grated circuit (IC) fabrication incurs more ...