The high-order Σ-Δ modulator is an appropriate approach for high-bandwidth, high-resolution A/D conversion. However, non-ideal effects such as the finite op-amp gain and the capacitor mismatch have great impacts on its performance at a low oversampling ratio. To achieve greater performance under the inevitable non-ideal effects, we explore several multiple-bit schemes, based on our CIQE high-order Σ-Δ architecture, to remove the non-ideal deterioration. Design rules of these multiple-bit schemes are developed and verified by extensive simulations.link_to_subscribed_fulltex
This paper presents a 3rd order 1.5-bit ΣΔ modulator with distributed feedback and local resonator f...
Oversampling and noise-shaping techniques, such as Σ ∆ modula-tion, have an inherent tradeoff betwee...
ΣΔ technique has always been the popular choice for designing high resolution data converters due to...
This paper presents a ΣΔ modulator (ΣΔM) which combines single-bit and multi-bit quantization in a c...
ΣΔ modulators are a well appreciated A/D converter choice for implementing the A/D conversion in rec...
A wideband 2-1-1 cascaded ΣΔ modulator with a single-bit quantizer in the two first stages and a 4-b...
Abstract:- This paper presents a study of the effect of settling error due to finite gain-bandwidth ...
http://digital.csic.es/bitstream/10261/3598/1/Higher_order_cascade.pdfThe use of Sigma-Delta (Σ∆) mo...
Fourth-order cascade ΣΔ modulators are very well suited for IC implementation using analog sampled-d...
设计一种新型低非线性失真拓扑的7阶1-bitΣ-Δ调制器,该调制器可以直接用于模拟音频信号输入带反馈的D类功率放大器中。通过仿真表明,调制器的最大稳定输入值可以达到0.9,信噪比可达到130 dB以上...
This paper proposes an architecture design approach for a wideband continuous-time (CT) ΣΔ modulator...
In this paper a systematic design methodology for high-order multi-bit continuous-time Delta-Sigma m...
An arbitrary order sigma-delta modulator cascude architecture is presented with only I-bit loss of ...
[[abstract]]We propose a multistage fourth order sigma-delta (ΣΔ) modulator with reduced sensitivity...
We present a ΣΔ modulator designed for ADSL applications in a 0.3Sμm CMOS pure digital technology. I...
This paper presents a 3rd order 1.5-bit ΣΔ modulator with distributed feedback and local resonator f...
Oversampling and noise-shaping techniques, such as Σ ∆ modula-tion, have an inherent tradeoff betwee...
ΣΔ technique has always been the popular choice for designing high resolution data converters due to...
This paper presents a ΣΔ modulator (ΣΔM) which combines single-bit and multi-bit quantization in a c...
ΣΔ modulators are a well appreciated A/D converter choice for implementing the A/D conversion in rec...
A wideband 2-1-1 cascaded ΣΔ modulator with a single-bit quantizer in the two first stages and a 4-b...
Abstract:- This paper presents a study of the effect of settling error due to finite gain-bandwidth ...
http://digital.csic.es/bitstream/10261/3598/1/Higher_order_cascade.pdfThe use of Sigma-Delta (Σ∆) mo...
Fourth-order cascade ΣΔ modulators are very well suited for IC implementation using analog sampled-d...
设计一种新型低非线性失真拓扑的7阶1-bitΣ-Δ调制器,该调制器可以直接用于模拟音频信号输入带反馈的D类功率放大器中。通过仿真表明,调制器的最大稳定输入值可以达到0.9,信噪比可达到130 dB以上...
This paper proposes an architecture design approach for a wideband continuous-time (CT) ΣΔ modulator...
In this paper a systematic design methodology for high-order multi-bit continuous-time Delta-Sigma m...
An arbitrary order sigma-delta modulator cascude architecture is presented with only I-bit loss of ...
[[abstract]]We propose a multistage fourth order sigma-delta (ΣΔ) modulator with reduced sensitivity...
We present a ΣΔ modulator designed for ADSL applications in a 0.3Sμm CMOS pure digital technology. I...
This paper presents a 3rd order 1.5-bit ΣΔ modulator with distributed feedback and local resonator f...
Oversampling and noise-shaping techniques, such as Σ ∆ modula-tion, have an inherent tradeoff betwee...
ΣΔ technique has always been the popular choice for designing high resolution data converters due to...