Add to ORKGA 1.6 Gb/s receiver for optical communication has been designed and fabricated in a 0.25-μm CMOS process. This receiver has no transimpedance amplifier and uses the parasitic capacitor of the flip-chip bonded photodetector as an integrating element and resolves the data with a double-sampling technique. A simple feedback loop adjusts a bias current to the average optical signal, which essentially "AC couples" the input. The resulting receiver resolves an 11 μA input, dissipates 3 mW of power, occupies 80 μm x 50 μm of area and operates at over 1.6 Gb/s
Abstract-In circuits and systems for short distance communications optical receivers with monolithic...
Interconnect architectures which leverage high-bandwidth optical channels offer a promising solution...
Interconnect architectures which leverage high-bandwidth optical channels offer a promising solution...
the bit rate is limited by the sample bandwidth and input sensitivity of the sense amp, and not the ...
This paper describes a dense, high-speed, and low-power CMOS optical receiver implemented in a 65-nm...
An efficient baud rate clock and data recovery architecture is applied to a double sampling/integrat...
This paper presents the design and implementation of a CMOS 310Mb=s receiver for use in a multi-chan...
Optical interconnects have attracted great interest as data rates continue to increase. When compare...
A low-power receiver with a one-tap decision feedback equalization (DFE) was fabricated in 90-nm CMO...
An optical interconnect transceiver incorporates a 4-tap FIR TX to reduce VCSEL average current and ...
A low power receiver with a one tap DFE was fabricated in 90mm CMOS technology. The speculative equa...
The large demand for high-bandwidth communication systems has brought down the cost of optical syst...
An optical interconnect transceiver incorporates a 4-tap FIR TX to reduce VCSEL average current and ...
As computing systems and communication networks grow more complex, so is the need for higher bandwi...
With the increasing bandwidth requirements of computing systems and limitations on power consumption...
Abstract-In circuits and systems for short distance communications optical receivers with monolithic...
Interconnect architectures which leverage high-bandwidth optical channels offer a promising solution...
Interconnect architectures which leverage high-bandwidth optical channels offer a promising solution...
the bit rate is limited by the sample bandwidth and input sensitivity of the sense amp, and not the ...
This paper describes a dense, high-speed, and low-power CMOS optical receiver implemented in a 65-nm...
An efficient baud rate clock and data recovery architecture is applied to a double sampling/integrat...
This paper presents the design and implementation of a CMOS 310Mb=s receiver for use in a multi-chan...
Optical interconnects have attracted great interest as data rates continue to increase. When compare...
A low-power receiver with a one-tap decision feedback equalization (DFE) was fabricated in 90-nm CMO...
An optical interconnect transceiver incorporates a 4-tap FIR TX to reduce VCSEL average current and ...
A low power receiver with a one tap DFE was fabricated in 90mm CMOS technology. The speculative equa...
The large demand for high-bandwidth communication systems has brought down the cost of optical syst...
An optical interconnect transceiver incorporates a 4-tap FIR TX to reduce VCSEL average current and ...
As computing systems and communication networks grow more complex, so is the need for higher bandwi...
With the increasing bandwidth requirements of computing systems and limitations on power consumption...
Abstract-In circuits and systems for short distance communications optical receivers with monolithic...
Interconnect architectures which leverage high-bandwidth optical channels offer a promising solution...
Interconnect architectures which leverage high-bandwidth optical channels offer a promising solution...