As the feature size continues scaling down, interconnects become the major contributor of signal delay. Since interconnects are mainly determined by placement and routing, these two stages play key roles to achieve high performance. Historically, they are divided into two separate stages to make the problem tractable. Therefore, the routing information is not available during the placement process. Net models such as HPWL, are employed to approximate the routing to simplify the placement problem. However, the good placement in terms of these objectives may not be routable at all in the routing stage because different objectives are optimized in placement and routing stages. This inconsistancy makes the results obtained by the two-step optim...
This paper presents a novel method to reduce routing congestion during placement stage. The proposed...
In VLSI physical design, the routing task consists of using over-the-cell metal wires to connect pin...
With aggressive scaling of semiconductor manufacturing technology in recent decades, the complexity ...
Abstract—In nanometer-scale VLSI technologies, several interconnect is-sues like routing congestion ...
As the feature size continues scaling down, interconnects become the major contributor of signal del...
As technology advances, the effect of intra-module delays become less significant, while the effect ...
The placement step in VLSI physical design flow deals with the problem of determining the locations ...
Most existing performance-driven and clock routing algorithms construct optimal routing topology for...
In advanced technology nodes, aggressive device scaling along with fundamental physical (lithographi...
Topic of this dissertation is the fast placement of hypergraph nodes into multi-dimensional grids. H...
The computational requirements for high quality synthesis, analysis, and verification of VLSI design...
In this paper, we propose a new approach for VLSI intercon-nect global routing that can optimize bot...
Interconnect delay has become a critical factor in determining the performance of integrated circuit...
In this paper, we study the interconnect layout optimization problem under a higher order resistance...
Most existing performance-driven and clock routing al-gorithms construct optimal routing topology fo...
This paper presents a novel method to reduce routing congestion during placement stage. The proposed...
In VLSI physical design, the routing task consists of using over-the-cell metal wires to connect pin...
With aggressive scaling of semiconductor manufacturing technology in recent decades, the complexity ...
Abstract—In nanometer-scale VLSI technologies, several interconnect is-sues like routing congestion ...
As the feature size continues scaling down, interconnects become the major contributor of signal del...
As technology advances, the effect of intra-module delays become less significant, while the effect ...
The placement step in VLSI physical design flow deals with the problem of determining the locations ...
Most existing performance-driven and clock routing algorithms construct optimal routing topology for...
In advanced technology nodes, aggressive device scaling along with fundamental physical (lithographi...
Topic of this dissertation is the fast placement of hypergraph nodes into multi-dimensional grids. H...
The computational requirements for high quality synthesis, analysis, and verification of VLSI design...
In this paper, we propose a new approach for VLSI intercon-nect global routing that can optimize bot...
Interconnect delay has become a critical factor in determining the performance of integrated circuit...
In this paper, we study the interconnect layout optimization problem under a higher order resistance...
Most existing performance-driven and clock routing al-gorithms construct optimal routing topology fo...
This paper presents a novel method to reduce routing congestion during placement stage. The proposed...
In VLSI physical design, the routing task consists of using over-the-cell metal wires to connect pin...
With aggressive scaling of semiconductor manufacturing technology in recent decades, the complexity ...