The end product of this research is the development of an efficient method of interconnecting hundreds of processors via buses that use techniques known in local area network systems. The buses provide a high bandwidth channel with a token bus protocol that significantly reduces the latency found in most interconnection systems. The system consists of a bus interface unit to provide an interface between each processor and the buses. The system provides multiple buses to increase the system throughput and reliability. The token bus protocol is based on the IEEE 802.4 protocol with modifications to facilitate the use of multiple buses;The dissertation describes the interconnection network and the performance of the network. The bus interface ...
Abstract: In order to build large shared-memory multiprocessor systems that take advantage of curren...
[[abstract]]The performance of multiple-bus networks with full bus-memory connection, single bus-mem...
This report describes two possible implementations for a bus interconnect structure which would be ...
The end product of this research is the development of an efficient method of interconnecting hundre...
New multiprocessor architectures are needed to support modern broadband applications, because tradit...
[[abstract]]The authors study the performance of multiprocessor systems employing multiple buses as ...
[[abstract]]The authors study the performance of multiprocessor systems employing multiple buses as ...
The purpose of this paper is to present the differences in hardware, installation, operation cost an...
[[abstract]]The performance of multiple-bus networks with full bus-memory connection, single bus-mem...
A new protocol, the unique token protocol, for reliably transporting data in a network is described....
Abstract-- A new class of interconnection networks is proposed for processor to memory communication...
[[abstract]]The performance of multiple-bus networks with full bus-memory connection, single bus-mem...
Multistage interconnection networks are very promising for shared-memory multiprocessor systems. The...
The performance evaluation of multiprocessor interconnects cannot be divorced from issues of traffic...
The principal modelling and simulation features of multistage interconnection networks operating in ...
Abstract: In order to build large shared-memory multiprocessor systems that take advantage of curren...
[[abstract]]The performance of multiple-bus networks with full bus-memory connection, single bus-mem...
This report describes two possible implementations for a bus interconnect structure which would be ...
The end product of this research is the development of an efficient method of interconnecting hundre...
New multiprocessor architectures are needed to support modern broadband applications, because tradit...
[[abstract]]The authors study the performance of multiprocessor systems employing multiple buses as ...
[[abstract]]The authors study the performance of multiprocessor systems employing multiple buses as ...
The purpose of this paper is to present the differences in hardware, installation, operation cost an...
[[abstract]]The performance of multiple-bus networks with full bus-memory connection, single bus-mem...
A new protocol, the unique token protocol, for reliably transporting data in a network is described....
Abstract-- A new class of interconnection networks is proposed for processor to memory communication...
[[abstract]]The performance of multiple-bus networks with full bus-memory connection, single bus-mem...
Multistage interconnection networks are very promising for shared-memory multiprocessor systems. The...
The performance evaluation of multiprocessor interconnects cannot be divorced from issues of traffic...
The principal modelling and simulation features of multistage interconnection networks operating in ...
Abstract: In order to build large shared-memory multiprocessor systems that take advantage of curren...
[[abstract]]The performance of multiple-bus networks with full bus-memory connection, single bus-mem...
This report describes two possible implementations for a bus interconnect structure which would be ...