Processor hardware has been architected with the assumption that most data access patterns would be linearly spatial in nature. But, most applications involve algorithms that are designed with optimal efficiency in mind, which results in non-spatial, multi-dimensional data access. Moreover, this data view or access pattern changes dynamically in different program phases. This results in a mismatch between the processor hardware\u27s view of data and the algorithmic view of data, leading to significant memory access bottlenecks. This variation in data views is especially more pronounced in applications involving large datasets, leading to significantly increased latency and user response times. Previous attempts to tackle this problem were p...
In the past few years, code optimization has become a major field of research. Many efforts have bee...
Recently, reconfigurable architectures, which outperform DSP processors, have become important. Alth...
We present a compilation technique that targets realtime applications running on embedded processors...
Processor hardware has been architected with the assumption that most data access patterns would be ...
Energy consumption is a primary concern of current day computing systems -- from handheld battery op...
We present and evaluate a simple, yet efficient dynamic optimization technique that increases memory...
Many High-Performance Computing (HPC) applications spend a significant portion of their execution ti...
Abstract. Given the size of today’s data, out-of-core visualization tech-niques are increasingly imp...
In this paper, we provide a novel compile-time data remapping algorithm that runs in linear time. ...
The memory system is a major bottleneck in achieving high performance and energy efficiency for vari...
The advent of data proliferation and electronic devices gets low execution time and energy consumpti...
Dynamic optimization has been proposed to overcome many limitations of static optimization, such as ...
Recently, CPUs with an identical ISA tend to have different microarchitectures, different computatio...
The rising complexity, customization and short time to market of modern digital systems requires aut...
Many data-intensive applications exhibit poor temporal and spatial locality and perform poorly on co...
In the past few years, code optimization has become a major field of research. Many efforts have bee...
Recently, reconfigurable architectures, which outperform DSP processors, have become important. Alth...
We present a compilation technique that targets realtime applications running on embedded processors...
Processor hardware has been architected with the assumption that most data access patterns would be ...
Energy consumption is a primary concern of current day computing systems -- from handheld battery op...
We present and evaluate a simple, yet efficient dynamic optimization technique that increases memory...
Many High-Performance Computing (HPC) applications spend a significant portion of their execution ti...
Abstract. Given the size of today’s data, out-of-core visualization tech-niques are increasingly imp...
In this paper, we provide a novel compile-time data remapping algorithm that runs in linear time. ...
The memory system is a major bottleneck in achieving high performance and energy efficiency for vari...
The advent of data proliferation and electronic devices gets low execution time and energy consumpti...
Dynamic optimization has been proposed to overcome many limitations of static optimization, such as ...
Recently, CPUs with an identical ISA tend to have different microarchitectures, different computatio...
The rising complexity, customization and short time to market of modern digital systems requires aut...
Many data-intensive applications exhibit poor temporal and spatial locality and perform poorly on co...
In the past few years, code optimization has become a major field of research. Many efforts have bee...
Recently, reconfigurable architectures, which outperform DSP processors, have become important. Alth...
We present a compilation technique that targets realtime applications running on embedded processors...