VLSI Architecture for Steady-State Genetic Algorithms

Genetic Algorithms (GA) are a class of stochastic optimization algorithms based on natural evolution. We have designed \u22GAP\u22 (Genetic Algorithm Processor), a general-purpose VLSI for GA. It is based on Steady-State GA, and achieves better performance by pipeline parallelization than other GA-VLSIs, which are based on conventional generation-based GA. Moreover, GAP introduces \u22Simplified Tournament Selection\u22 scheme for implementing the selection module. This scheme is proved much simpler, faster, and better in convergence compared to \u22Roulette Wheel Selection\u22 scheme, which is widely used in other GA-VLSI\u27s