Methodology for early estimation of hierarchical routing resources in 3D FPGAs

Power becomes an ever-increasing concern due to the growing design complexity and the shrinking process technology. Power estimation at an early stage of electronic design automation (EDA) flow is essential in order to handle the design issues much earlier. Also power due to the routing resources is a dominant in field-programmable gate arrays (FPGAs). In this paper, we introduce a methodology for early estimation of hierarchical routing resources targeting power-aware EDA flow for three-dimensional FPGAs. We analyze the behavior of wire segments on a two-dimensional plane to derive a model for estimating the required number of routing segments in a 3D FPGA for a given circuit. For a number of MCNC benchmark circuits, the proposed methodology is validated against the output of TPR, an academic 3D place and route tool for FPGAs. We achieved a mean error of 29.04% for segmented wires; single-length, double-length and hex-length segments among all 14 selected benchmark circuits