Mitigating Performance Loss in Aggressive DVS Using Dual-Sensing Flip-Flops

VLSI-SoC 2008 : Rhodes Island, Greece : October 13-15, 2008Traditional worst-case design is becoming much difficult. The increase in parameter variations requires large design margins. However since the worst-case situations do not always occur, the design margin is often overestimated. To eliminate the excessive design margin, designers should focus on typical case rather than worst case. We are investigating canary logic that is one of the typical-case designs. The canary logic can eliminate the excessive design margin by combined with Dynamic Voltage Scaling (DVS) system. A naive combination of the canary and the DVS suffers serious performance loss due to useless voltage scaling. In this paper, we show where the performance loss comes from and improve the canary logic to eliminate the excessive design margin without performance loss