Cascading Dependent Operations for Mitigating Timing Variability

As semiconductor technologies are aggressively advanced, the problem of parameter variations is emerging. Process variations in transistors affect circuit delay, resulting in serious yield loss. This paper investigates to exploit the statistical features in circuit delay and to cascade dependent ALU operations for reducing variations, From the statistical static timing analysis in circuit level and the performance evaluation in processor level, this paper tries to unveil how efficiently ALU cascading improves performance yield of processors. It is found that innovations are required for managing parameter variations in the microarchitecture level