Energy Consumption Evaluation of an Adaptive Extensible Processor

Second Annual Reconfigurable and Adaptive Architecture Workshop (RAAW-2) : Dec. 1, 2007 : Chicago,Illinois, USAMost embedded systems rely on batteries as their source of energy, and hence, low power consumption is inherently essential for them. In processor-based embedded systems, a large portion of power is consumed for accessing instruction memories (including on-chip caches and off-chip memories), register-file, and also in the clock-distribution tree. Encapsulating critical computation subgraphs as applicationspecific instruction set extensions is an effective technique to reduce above-mentioned accesses and execution time (clock energy) and consequently, enhance the energy efficiency of these systems. However, the addition of custom functional units to the base processor is required to support the execution of custom instructions, which due to the increase of manufacturing and design costs in new nanometer-scale technologies and shorter time-to-market it is becoming an issue. To address these issues, in our proposed approach, the custom functional units are replaced with a reconfigurable functional unit and instruction customization is done after chip-fabrication. Therefore, while maintaining the flexibility of a conventional microprocessor, the energy reduction feature of customization is utilized for enhancing the energy efficiency. Our reconfigurable functional-unit is capable of executing custom instructions with multiple exits, resulting in 15% more energy saving compared to the single-exit counterpart. Moreover, two custom instruction invocation techniques are compared in terms of energy saving. Experimental results show up to 79% reduction (37% on average) energy saving on MiBench benchmark suit